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72V8985JG8

P1-P3P4-P6P7-P9P10-P12P13-P14
7
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Connection Memory High
Connection Memory Low
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
100001 100010 111111
Data Memory
0 0
0
0
0 0
1
1
0 1
0
2
0 1
1 3
1 0
0 4
1 0
1 5
1 1
0 6
1 1 1
7
Stream
0 1
1
0
1 1
Control Register
CR
b
7
External Address Bits A5-A0
5707
drw08
100000
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CR
b
6CR
b
5CR
b
4CR
b
3CR
b
2CR
b
1CR
b
0
CR
b
4CR
b
3
CR
b
2CR
b
1CR
b
0
Figure 5. Addressing Internal Memories
8
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
TABLE 4
CONNECTION MEMORY HIGH
TABLE 5
CONNECTION MEMORY LOW
TABLE 3
CONTROL REGISTER
Bit Name Description
7 SM (Split Memory) When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when
the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations.
6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in high-
impedance. When 0, the Connection Memory bits for each channel determine what is output.
5 unused
4-3 MS1-MS0 0-0 - Not to be used.
(Memory Select Bits) 0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0 STA2-0 The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
(Stream Address Bits) subsection of memory made accessible for subsequent operations.
SM PE X MS1 MS0 STA2 STA1 STA0
76543210
x = don't care
Bit Name Description
7,5,4,3 unused
6 V/C (Variable/Constant This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.
Throughput Delay Mode)
2 CS When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
(Channel Source) and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
1 CCO (CCO Bit) This bit drives a bit time on the CCO output pin.
0 OE (Output Enable) This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to
be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it.
X V/CXXXCSCCOOE
76543210
x = don't care
Bit Name Description
7-5 SAB2-0
(1)
These three bits are used to select eight source streams for the Connection.
(Source Stream Address Bits)
4-0
(1)
CAB2-0
(1)
These five bits are used to select 32 different source channels for the Connection (the stream where the channel
(Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.
SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.
76543210
9
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
Test Point
Output
Pin
C
L
GND
S
1
RL
VCC
GND
5707 drw09
S2
S1 is open circuit except when testing output
levels or high impedance states.
S2 is switched to V
CC or GND when testing
output levels or high impedance states.
Figure 6. Output Load
RECOMMENDED OPERATING
CONDITIONS
DC ELECTRICAL CHARACTERISTICS
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Symbol Parameter Min. Max. Unit
Vcc Symbol Voltage -0.3 5.0 V
Vi Voltage on Digital Inputs GND - 0.3 V
CC +0.5 V
V
O Voltage on Digital Outputs GND - 0.3 VCC +0.3 V
I
O Current at Digital Outputs 20 mA
T
S Storage Temperature -55 +125 ° C
P
D Package Power Dissapation 1 W
Symbol Parameter Min. Typ.
(1)
Max. Unit
V
CC Positive Supply 3.0 3.3 3.6 V
V
I Input Voltage 0 5.25 V
T
OP Operating Temperature -40 25 +85 ° C
Commercial
Symbol Parameter Min. Typ.
(1)
Max. Units Test Conditions
I
CC Supply Current 3 5 mA Outputs Unloaded
V
IH Input High Voltage 2.0  V
V
IL Input Low Voltage 0.8 V
I
IL Input Leakage (Inputs) 15 µAVI between GND and VCC
CI Input Capacitance 10 pF
V
OH Output High Voltage 2.4  VIOH = 10mA
I
OH Output High Current 10  mA Sourcing. VOH = 0.8V
V
OL Output Low Voltage 0.4 V IOL = 5mA
I
OL Output Low Current 5  mA Sinking. VOL = 0.4V
I
OZ High Impedance Leakage  5 µAVO between GND and VCC
CO Output Pin Capacitance 10 pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only a functional operation
of the device at these or any conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
P1-P3P4-P6P7-P9P10-P12P13-P14

72V8985JG8

Mfr. #:
Buy 72V8985JG8
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 3.3V 256 X 256 TSI SWITCH
Lifecycle:
New from this manufacturer.
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