5
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8985, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
To summarize, any input time slot from input frame N will be always switched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
The IDT72V8985 microprocessor port is a non-multiplexed bus architec-
ture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address
input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel
microport allows the access to the Control Registers, Connection Memory Low,
Connection Memory High, and the Data Memory. All locations are read/written
except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (DTA). In the IDT72V8985
device, the DTA output provides a maximum acknowledgment delay of 800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
SOFTWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8985 Data and
Connect memories. See Figure 5 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
Stream Address bits define internal memory subsections corresponding to input
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5) are output on the output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every
Connection Memory High (CMH, see Table 4) locations were set to HIGH,
regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connection
Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH,
the associated TX output channel is in Processor Mode. If bit 2 of the CMH is
LOW, then the contents of the CML define the source information (stream and
channel) of the time slot that is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) for that particular channel.
The contents of bit 1 (CCO) of each Connection Memory High Location (see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/
s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit
on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on
the CCO output is transmitted LOW. The contents of the 256 CCO bits of the CMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TX streams. For example, the contents of CCO bit in position 0 (corresponding
to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.
INITIALIZATION
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two Connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
The reset pin is designed to be used with board reset circuitry. During reset
the TX serial streams will be put into high-impedance and the state of internal
registers and counters will be reset. As the connection memory can be in any
state after a power up, the ODE pin should be used to hold the TX streams in
high-impedance until the per-channel output enable control in the connection
memory high is appropriately programmed. The main difference between ODE
and reset is, reset alters the state of the registers and counters where as ODE
controls only the high-impedance state of the TX streams. RESET input is only
provided on the SSOP packages.
TABLE 1 VARIABLE DELAY MODE
Input Channel Output Channel Throughput Delay
n m=n, n+1 or n+2 m-n+32 time slot
n m>n+2 m-n time slot
n m<n 32-(n-m) time slot
TABLE 2 ADDRESS MAPPING
A5 A4 A3 A2 A1 A0 LOCATION
0 X X X 0 0 Control Register
100000 Channel 0
100001 Channel 1
1
••••• •
1 ••••• •
1 ••••• •
1 ••••• •
1 ••••• •
111111 Channel 31
