6.422
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
The QDRII has echo clocks, which provide the user with a clock
that is precisely timed to the data output, and tuned with matching imped-
ance and signal quality. The user can use the echo clock for down-
stream clocking of the data. Echo clocks eliminate the need for the user
to produce alternate clocks with precise timing, positioning, and signal
qualities to guarantee data capture. Since the echo clocks are gener-
ated by the same source that drives the data output, the relationship to
the data is not significantly affected by voltage, temperature and process,
as would be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
DDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in four word bursts, with
addressing capability to the burst level.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx), the address, first
and third words of the data burst during a write operation. The K clock
is used to clock in the control signals (BWx) and the second and fourth
words of the data burst during a write operation. The K and K clocks are
also used internally by the SRAM. In the event that the user disables the
C and C clocks, the K and K clocks will be used to clock the data out of
the output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the QDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the QDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.
The C and second data word of the burst will also correspond. The third
and fourth data words will follow on the next clock cycle of C and C,
respectively.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the 4 words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte write signals can be used to prevent writing any individual bytes, or
combined to prevent writing one word of the burst.
Read and write operations may be interleaved with each occurring
on every other clock cycle. In the event that two reads or two writes are
requested on adjacent clock cycles, the operation in progress will com-
plete and the second request will be ignored. In the event that both a
read and write are requested simultaneously, the read operation will win
and the write operation will be ignored.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and presenting the designated write address to the address bus. The
QDRII SRAM will receive the address on the rising edge of clock K. On
the following rising edge of K clock, the QDRII SRAM will receive the first
data item of the four word burst on the data bus. Along with the data, the
byte write (BWx) inputs will be accepted, indicating which bytes of the
data inputs should be written to the SRAM. On the following rising edge
of K, the next word of the write burst and BWx will be accepted. The
subsequent K and K rising edges will receive the last two words of the
four word burst, with their BWx enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
