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IDT71P74604S250BQ8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.424
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Symbol Pin Function Description
Doff
Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the
DLL turned off will be different from those listed in this data sheet. There will be an increased
propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The
propagation delay is not a tested parameter, but will be similar to the propagation delay of other
SRAM devices in this speed grade.
TDO Output TDO pin for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS Input TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
NC No Connect No connects inside the package. Can be tied to any voltage level
V
REF
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
V
DD
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
V
SS
Ground Ground for the device. Should be connected to ground of the system.
V
DDQ
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for
HSTL or scaled to the desired output voltage.
6111 tbl 02b
Pin Definitions continued
6.42
5
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Configuration IDT71P74804 (1M x 18)
1234567891011
A
CQ
V
SS/
SA
(3)
NC/
SA
(1)
WBW
1
K
NC
R
SA
V
SS/
SA
(2)
CQ
B
NC Q
9
D
9
SA NC K
BW
0
SA NC NC Q
8
C
NC NC D
10
V
SS
SA NC SA V
SS
NC Q
7
D
8
D
NC D
11
Q
10
V
SS
V
SS
V
SS
V
SS
V
SS
NC NC D
7
E
NC NC Q
11
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC D
6
Q
6
F
NC Q
12
D
12
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC NC Q
5
G
NC D
13
Q
13
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC NC D
5
H
Doff
V
REF
V
DDQ
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
REF
ZQ
J
NC NC D
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC Q
4
D
4
K
NC NC Q
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC D
3
Q
3
L
NC Q
15
D
15
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC NC Q
2
M
NC NC D
16
V
SS
V
SS
V
SS
V
SS
V
SS
NC Q
1
D
2
N
NC D
17
Q
16
V
SS
SA SA SA V
SS
NC NC D
1
P
NC NC Q
17
SASA C SASANCD
0
Q
0
R
TDO TCK SA SA SA
C
SA SA SA TMS TDI
6111 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
6.426
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Pin Configuration IDT71P74604 (512K x 36)
165-ball FBGA Pinout
TOP VIEW
1234567891011
A
CQ
V
SS
/
SA
(4)
NC/
SA
(2)
WBW
2
KBW
1
R
NC/
SA
(1)
V
SS
SA
(3)
CQ
B
Q
27
Q
18
D
18
SA
BW
3
K
BW
0
SA D
17
Q
17
Q
8
C
D
27
Q
28
D
19
V
SS
SA NC SA V
SS
D
16
Q
7
D
8
D
D
28
D
20
Q
19
V
SS
V
SS
V
SS
V
SS
V
SS
Q
16
D
15
D
7
E
Q
29
D
29
Q
20
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
Q
15
D
6
Q
6
F
Q
30
Q
21
D
21
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
14
Q
14
Q
5
G
D
30
D
22
Q
22
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
13
D
13
D
5
H
Doff
V
REF
V
DDQ
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
REF
ZQ
J
D
31
Q
31
D
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
12
Q
4
D
4
K
Q
32
D
32
Q
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
12
D
3
Q
3
L
Q
33
Q
24
D
24
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
D
11
Q
11
Q
2
M
D
33
Q
34
D
25
V
SS
V
SS
V
SS
V
SS
V
SS
D
10
Q
1
D
2
N
D
34
D
26
Q
25
V
SS
SA SA SA V
SS
Q
10
D
9
D
1
P
Q
35
D
35
Q
26
SA SA C SA SA Q
9
D
0
Q
0
R
TDO TCK SA SA SA
C
SA SA SA TMS TDI
6111 tbl 12c
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDT71P74604S250BQ8

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IC SRAM 18M PARALLEL 165CABGA
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