6.4214
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register
0 0 1 IDCODE Identification register 2
0 1 0 SAMPLE-Z Boundary Scan Register 1
0 1 1 RESERVED Do Not Use 5
1 0 0 SAMPLE/PRELOAD Boundary Scan register 4
1 0 1 RESERVED Do Not Use 5
1 1 0 RESERVED Do Not Use 5
1 1 1 BYPASS Bypass Register 3
6111tbl 13
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI
when existing the Shift DR states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
Run Test Idle Select DR
Capture DR
Pause DR
Exit 2 DR
Update DR
Shift DR
Exit 1 DR
Select IR
Capture IR
Pause IR
Exit 2 IR
Update IR
Shift IR
Exit 1 IR
0
0
0
0
0
0
1
1
1
1
1
1
1
0
6111 drw 17
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg
.
Control Signal
s
TAP Controller
A,D
K,K
C,C
Q
CQ
CQ
TDI
TMS
TCK
TDO
6111 drw 18
S
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Ac-
cess Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Regis-
ter and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
