13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T4088/72T4098/72T40108/72T40118 support two different
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT input.
During Master Reset, if the FWFT pin is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not there
are any words present in the FIFO. It also uses the Full Flag function (FF) to
indicate whether or not the FIFO has any free space for writing. In IDT Standard
mode, every word read from the FIFO, including the first, must be requested
using the Read Enable (REN) and RCLK.
If the FWFT pin is HIGH during Master Reset, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, applying REN = LOW is not necessary. However, subsequent words
must be accessed using the Read Enable (REN) and RCLK.
Various signals, in both inputs and outputs operate differently depending on
which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags FF, PAF, PAE, and EF operate in the manner
outlined in Table 4. To write data into the FIFO, Write Enable (WEN) must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are listed in Table 3. This parameter
is also user programmable. See section on Programmable Flag Offset Loading.
Continuing to write data into the FIFO without performing read operations will
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (16,384-m) writes for the IDT72T4088,
(32,768-m) writes for the IDT72T4098, (65,536-m) writes for the IDT72T40108
and (131,072-m) writes for the IDT72T40118. The offset “m” is the full offset
value. The default setting for these values are listed in Table 3. This parameter
is also user programmable. See the section on Programmable Flag Offset
Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 16,384 writes for the IDT72T4088, 32,768 writes for the
IDT72T4098, 65,536 writes for the IDT72T40108 and 131,072 writes for the
IDT72T40118, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent
read operations will cause PAF to go HIGH at the conditions described in Table
4 If further read operations occur, without write operations, PAE will go LOW
when there are n words in the FIFO, where n is the empty offset value.
Continuing read operations will cause the FIFO to become empty. Then the last
word has been read from the FIFO, the EF will go LOW inhibiting further read
operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs. IDT Standard mode is available when the device is
configured in both Single Data Rate and Double Data Rate mode.
Relevant timing diagrams for IDT Standard mode can be found in Figure 10,
11, 12, 13, 14, 15, 16, 17, 18 and 23.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags OR, IR, PAE, and PAF operate in the manner
outlined in Table 5. To write data into to the FIFO, WEN must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR
)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are listed in Table 3. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
Continuing to write data into the FIFO without performing read operations will
cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads
are performed, the PAF will go LOW after (16,385-m) writes for the IDT72T4088,
(32,769-m) writes for the IDT72T4098, (65,537-m) writes for the IDT72T40108
and (131,073-m) writes for the IDT72T40118. The offset “m” is the full offset
value. The default setting for these values are listed in Table 3. This parameter is
also user programmable. See the section on Programmable Flag Offset Loading.
When the FIFO is full, the Input Ready (IR) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, IR will go LOW after D writes
to the FIFO. D = 16,385 writes for the IDT72T4088, 32,769 writes for the
IDT72T4098, 65,537 writes for the IDT72T40108 and 131,073 writes for the
IDT72T40118, respectively. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause IR to go HIGH. Subsequent
read operations will cause PAF to go HIGH at the conditions described in Table
5. If further read operations occur, without write operations, PAE will go LOW
when there are n words in the FIFO, where n is the empty offset value.
Continuing read operations will cause the FIFO to become empty. Then the last
word has been read from the FIFO, the OR will go HIGH inhibiting further read
operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-buffered
and the IR flag output is double register-buffered. FWFT mode is only available
when the device is configured in Single Data Rate mode.
Relevant timing diagrams for IDT Standard mode can be found in Figure 19,
20, 21, 22 and 24.
