6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
PIN DESCRIPTION
BM
(1)
Bus-Matching LVTTL During Master Reset, this pin along with IW and OW selects the bus sizes for both write and read
(K2) INPUT ports.
D0-D39 Data Inputs HSTL-LVTTL Data inputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused input pins are in a don’t
(See Pin No. INPUT care state. The data bus is sampled on both rising and falling edges of WCLK when WEN is enabled and
table for details) DDR Mode is enabled or on the rising edges of WCLK only in SDR Mode.
EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory
(M14) Output Ready OUTPUT is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data
available at the outputs.
ERCLK Echo Read HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs.
(L16) Clock OUTPUT
EREN Echo Read HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK.
(K16) Enable OUTPUT
FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
(H3) Input Ready OUTPUT empty. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available
for writing to the FIFO memory.
FSEL0
(1)
Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 will select the default offset values for the programmable
(J3) INPUT flags PAE and PAF. There are four possible settings available.
FSEL1
(1)
Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 will select the default offset values for the programmable
(J2) INPUT flags PAE and PAF. There are four possible settings available.
FWFT First Word Fall LVTTL During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in
(G2) Through INPUT DDR mode. In SDR mode, the first word will always fall through on the rising edge.
HSTL
(1)
HSTL Select LVTTL This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this
(B7) INPUT input must be tied HIGH, otherwise it must be tied LOW and cannot toggle during operation.
IW
(1)
Input Width LVTTL During Master Reset, this pin along with OW and BM, selects the bus width of the read and write port.
(K1) INPUT
MARK Mark Read HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
(E14) Pointer for INPUT operation will reset the read pointer to this position. There is an unlimited number to times to set the mark
Retransmit location, but only the most recent location marked will be acknowledged.
MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Master
(J1) INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, and
programmable flag default settings.
OE Output Enable HSTL-LVTTL When HIGH, data outputs Q0-Q39 are in high impedance. When LOW, the data outputs Q0-Q39 are enabled.
(G15) INPUT No other outputs are affected by OE.
OW
(1)
Output Width LVTTL During Master Reset, this pin along with IW and BM, selects the bus width of the read and write port.
(L3) INPUT
PAE Programmable HSTL-LVTTL PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is
(L15) Almost-Empty OUTPUT stored in the Empty Offset register. PAE goes LOW if the number of words in the FIFO memory is less than
Flag offset n.
PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored
(G3) Almost-Full Flag OUTPUT in the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than
or equal to m.
PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Partial
(K3) INPUT Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected.
Q0-Q39 Data Outputs HSTL-LVTTL Data outputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused output pins should not
(See Pin No. OUTPUT be connected. The output data is clocked on both rising and falling edges of RCLK when REN is enabled
table for details) and DDR Mode is enabled or on the rising edges of RCLK only in SDR Mode.
RCLK Read Clock HSTL-LVTTL Input clock when used in conjunction with REN for reading data from the FIFO memory and output register.
(G16) INPUT
Symbol & Name I/O TYPE Description
Pin No.
