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IDT72T40108L6-7BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
PIN DESCRIPTION (CONTINUED)
RCS Read Chip Select HSTL-LVTTL RCS provides synchronous enable/disable control of the read port and High-Impedance control of the
(F14) INPUT Qn data outputs, synchronous to RCLK. When using RCS the OE pin must be tied LOW. During Master
or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
REN Read Enable HSTL-LVTTL When LOW and in DDR mode, REN along with a rising and falling edge of RCLK will send data in FIFO
(F16) INPUT memory to the output register and read the current data in output register. In SDR mode data will only be
read on the rising edge of RCLK only.
RSDR
(1)
Read Single Data LVTTL When LOW, this input pin sets the read port to Single Data Clock mode. When HIGH, the read port will operate
(L2) Rate INPUT in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during operation.
RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the read pointer to the first location in memory. EF flag
(F15) INPUT is set to LOW (OR to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not
affected. If a mark has been set via the MARK input pin, then the read pointer will initialize to the mark location
when RT is asserted.
SCLK Serial Clock LVTTL A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided
(H15) INPUT that SEN is enabled. A rising edge of SCLK will also read data out of the offset registers provided that SREN
is enabled.
SEN Serial Input HSTL-LVTTL SEN used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets.
(J15) Enable INPUT
SREN Serial Read HSTL-LVTTL SREN used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets.
(J16) Enable INPUT
SI Serial Input HSTL-LVTTL This input pin is used to load serial data into the programmable flag offsets. Used in conjunction with SEN
(H16) INPUT and SCLK.
SO Serial Output HSTL-LVTTL This output pin is used to read data from the programmable flag offsets. Used in conjunction with SREN
(K15) OUTPUT and SCLK.
TCK
(2)
JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
(F1) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
TDI
(2)
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
(E2) Input INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(2)
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
(F3) Output OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register,
ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-
DR and SHIFT-IR controller states.
TMS
(2)
JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
(F2) Select INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
(2)
JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
(E3) INPUT automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for
five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-
impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied
with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be
tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
WCLK Write Clock HSTL-LVTTL Input clock when used in conjunction with WEN for writing data into the FIFO memory.
(G1) INPUT
WCS Write Chip Select HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
(H2) INPUT
WEN Write Enable HSTL-LVTTL When LOW and in DDR mode, WEN along with a rising and falling edge of WCLK will write data into the
(H1) INPUT FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
Symbol & Name I/O TYPE Description
Pin No.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
PIN DESCRIPTION (CONTINUED)
Symbol & Name I/O TYPE Description
Pin No.
WSDR
(1)
Write Single Data LVTTL When LOW, this input pin sets the write port to Single Data Clock mode. When HIGH, the write port will
(L1) Rate INPUT operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle
during operation.
V
CC +2.5V Supply INPUT There are Vcc supply inputs and must be connected to the 2.5V supply rail.
(See below)
V
DDQ O/P Rail Voltage INPUT This pin should be tied to the desired voltage rail for providing power to the output drivers. Nominally 1.5V
(See below) or 1.8V for HSTL, 2.5V for LVTTL.
GND Core Ground Pin INPUT These are Ground pins are for the core device and must be connected to the GND rail.
(See below)
Vref Reference INPUT This is a Voltage Reference input and must be connected to a voltage level determined in the
(T3) Voltage Recommended DC Operating Conditions section. This provides the reference voltage when using HSTL
class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
PIN NUMBER TABLE
Symbol Name I/O TYPE Pin Number
D0-39 Data Inputs HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,
INPUT D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3, D20-N2, D21-P2, D22-R2,
D23-N1, D24-P1, D25-R1, D26-N3, D(27-29)-M(1-3), D30-E1, D(31-33)-D(3-1), D34-C1,
D(35,36)-B(1,2), D37-C2, D38-A3, D39-B3
Q0-39 Data Outputs HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14
OUTPUT Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10,
Q(20,21)-C(14,15), Q(22,23)-B(15,16), Q24-C16, Q(25-27)-D(16-14), Q(28,29)-E(16,15),
Q(30,31)-M(15,16), Q(32-34)- N(14-16), Q(35-37)-P(14-16), Q(38,39)-R(15,16)
VCC +2.5V Supply INPUT A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)
VDDQ O/P Rail Voltage INPUT A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),
P(10-13), T(15,16)
GND Ground Pin INPUT A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),
P(4,8,9), R(8,9), T(8,9)
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 25-28 and Figures 5-7.
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
Symbol Rating Commercial Unit
V
TERM Terminal Voltage –0.5 to +3.6
(2)
V
with respect to GND
T
STG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol Parameter Min. Max. Unit
ILI Input Leakage Current –10 10 µA
ILO Output Leakage Current –10 10 µA
V
OH
(5)
Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V
I
OH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V
V
OL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V
I
CC1
(1,2)
Active VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA
I/O = HSTL — 60 mA
I/O = eHSTL — 60 mA
ICC2
(1)
Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA
I/O = HSTL — 50 mA
I/O = eHSTL — 50 mA
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. V
CC terminal only.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
(2,3)
Input VIN = 0V 10
(3)
pF
Capacitance
C
OUT
(1,2)
Output VOUT = 0V 10 pF
Capacitance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x 2N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
tA = 25°C, CL = capacitive load (pf)
4. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
5. Outputs are not 3.3V tolerant.
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.375 2.5 2.625 V
VDDQ Output Rail Voltage for I/Os 2.375 2.5 2.625 V
GND Supply Voltage 0 0 0 V
V
IH Input High Voltage ⎯ LVTTL 1.7 — 3.45 V
⎯ eHSTL VREF+0.2 — — V
⎯ HSTL VREF+0.2 — — V
V
IL Input Low Voltage ⎯ LVTTL -0.3 — 0.7 V
⎯ eHSTL — — VREF-0.2 V
⎯ HSTL — — VREF-0.2 V
VREF Voltage Reference Input ⎯ eHSTL 0.8 0.9 1.0 V
(HSTL only) ⎯ HSTL 0.68 0.75 0.9 V
TA Operating Temperature Commercial 0 — 70 °C
TA Operating Temperature Industrial -40 — 85 °C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

IDT72T40108L6-7BB

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IC FIFO DDR/SDR 6-7NS 208-BGA
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