MAX7357EUG+ Datasheet MAX7357ETG+T, MAX7358ETG+, MAX7357EUG+ | P10-P12

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

10 ______________________________________________________________________________________

Detailed Description

The MAX7356/MAX7357/MAX7358 devices are 1-to-8

C multiplexers/switches for connecting a large num-

ber of I

C components to a single master. The circuits

connect a main I

C bus to any combination of 8 extend-

ed I

C buses. They enable a master on the main bus to

isolate and communicate with devices or groups of

devices that may otherwise have slave address con-

flicts. Any extended bus can be connected or discon-

nected by control packets from the main I

C bus writing

to the main control register of these I

C switches.

The MAX7357/MAX7358 feature a built-in timer used to

monitor all extended buses, for lock-up conditions. If the

data line of any of these buses is low for more than

25ms, a lock condition is detected. An optional interrupt

can be generated through the bidirectional RST/INT pin.

The master can read the bus lock-up register to find out

which extended bus is locked up. The master can also

optionally enable the MAX7357 or MAX7358 to send a

flush-out sequence on the faulty channel. There is an

optional preconnection check that can be enabled,

which toggles the extended bus clock and data line low

then high to ensure that the downstream bus is not

locked high prior to connecting it to the host bus.

The bus lock-up detection and isolation features are

enabled by writing a unique series of I

C commands to

the MAX7357/MAX7358.

Power-On Reset

When power is applied to V

, an internal power-on

reset (POR) holds the MAX7356/MAX7357/MAX7358 in

a reset state until V

has reached V

POR

. At this point,

the reset condition is released and the MAX7356/

MAX7357/MAX7358 registers and I

C state machine

are initialized to their default states.

Basic Mode of Operation

The MAX7356/MAX7357/MAX7358 feature a basic

mode of operation. In basic mode, the device operates

solely as a collection of analog switches that enable

any combination of the extended buses (SC_, SD_)

to be connected to the host-side bus (SCL, SDA). Only

the switch control register is accessible in basic mode

of operation.

Enhanced Mode of Operation

(MAX7357/MAX7358)

The MAX7357 and MAX7358 feature an enhanced

mode of operation that enable features and registers

that are unavailable in the basic mode of operation.

When operating in enhanced mode, there are 7 regis-

ters available to the host. Features such as bus lock-up

detection, preconnection fault tests, and diagnostic

information are made available to the user. A special

sequence of commands can switch the MAX7357 or

MAX7358 from basic mode to enhanced mode, and a

simple write to the configuration register can switch the

devices from enhanced mode back to basic mode.

Entering Basic Mode from

Enhanced Mode

(MAX7357/MAX7358)

When the 7 registers of Table 2 are enabled, the

MAX7357 and MAX7358 can be put into basic mode by

setting bit B6 of the configuration register. When basic

mode is entered, the value of all registers return to their

POR value. B6 of the configuration register is also main-

tained to allow operation in basic mode. When in basic

mode, the MAX7357 and MAX7358 can be returned to

full feature mode by receiving a special sequence of

commands from the host as described below.

The sequence of I

C commands for enabling the

MAX7357 or MAX7358 enhanced features (bus lock-up

detection, isolation, and notification) as well as access

to the additional 6 registers consists of a write byte, a

read byte, another write byte, and another read byte

with no data bytes following any of these write or read

bytes, as shown in Figure 5. A write byte consists of

the 7-bit MAX7357 or MAX7358 device address fol-

lowed by a 0. A read byte consists of the 7-bit

MAX7357 or MAX7358 device address followed by a 1.

The special sequence begins with a START condition

and ends with a STOP condition. Repeated START

conditions are used to interconnect these write and

read bytes.

The complete special sequence of I

C commands

needs to be received by the MAX7357 or MAX7358 to

activate the enhanced mode.

ADDRESS OF MUX/SWT PARTS

START

0 A Sr ADDRESS OF MUX/SWT PART 0 A SrADDRESS OF MUX/SWT PART 1 A Sr ADDRESS OF MUX/SWT PART 1 A P

ACKNOWLEDGE FROM THE

MAX7357 OR MAX7358

ACKNOWLEDGE FROM THE

MAX7357 OR MAX7358

ACKNOWLEDGE FROM THE

MAX7357 OR MAX7358

ACKNOWLEDGE FROM THE

MAX7357 OR MAX7358

STOP

Figure 5. The Special Sequence of I

C Commands for Turning on the Full Feature

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

______________________________________________________________________________________ 11

Bus Lock-Up Detection, Isolation,

and Notification Operation

(MAX7357/MAX7358)

SDA Stuck Low

If either line of any downstream bus is low for a period

exceeding 25ms between t

and t

in Figure 6, the

MAX7357/MAX7358 detect a lock-up fault on that bus

and takes the action configured by the user. If the lock-

up is not on the main bus, SDA and SCL return to the

high state at the same time. The MAX7357 or MAX7358

then identifies which SD_ or SC_ is still pulled low. If the

optional interrupt function is enabled (by setting B0 of

the configuration register), an active-low interrupt is

generated at RST/INT.

If B4 in the configuration register is set to 1, then only

faults on connected buses cause the MAX7357 or

MAX7358 to disconnect all buses from each other.

When this is the case, faults detected on disconnected

buses set the flag in the lock-up status register, and, if

enabled, notify the host of the fault, but do not discon-

nect the buses from one another.

B1 of the configuration register enables the flush-out

sequence. If this bit is set to 1, the MAX7357 or

MAX7358 attempts to send a flush-out sequence over

the locked SD_ and SC_ pair (the sequence begins at

in Figure 6). If the flush-out sequence is successful,

the locked bus (SD_ and SC_) is released at t

(Figure

6). The I

C master (at SDA and SCL) reads the

MAX7357 or MAX7358 lock-up status register to iden-

tify the locked-up bus. If RST/INT is enabled as an

interrupt, it is released once a read command to the

lock-up indication register is received by the MAX7357

or MAX7358 (shown at t

in Figure 6). The RST/INT

can also be automatically released after a 1.6s delay

by setting bit 2 of the configuration register.

Preconnection Wiggle Test

(Stuck High Fault)

(MAX7357/MAX7358)

By setting bit B7 in the configuration register to 1, a pre-

connection wiggle test is enabled for all downstream

buses. This test only runs on the downstream bus when

the bus is selected through the switch control register.

Enabling this test does not affect any bus that is already

connected to the host bus; however, deselecting and

subsequently reselecting the bus will cause the test to

occur. The test is performed when the switch control reg-

ister bit (or bits if multiple buses are selected in the same

C transaction) toggles from 0 to 1 and a stop condition

is received. It consists of the MAX7357 or MAX7358

pulling the downstream clock line low, then the down-

stream data line low. Both lines are checked for a nomi-

nal low value, and then the clock line is released followed

by the data line (Note: This is an I

C stop condition and

is seen by any I

C devices connected to the extended

bus). If either the clock or data line (or both) fail to pull

low during the test, the MAX7357 or MAX7358 do not

allow that downstream bus to connect to the host. If the

optional interrupt notification bit is set (B0), the device

notifies the host that a fault has occurred. The I

C master

can then read the MAX7357 or MAX7358 registers to find

out which bus or buses caused the fault. Faults detected

by this test are stored in the preconnection fault register

(0x06). The stuck high Fault register is cleared once this

preconnection test.

Device Address

The MAX7356/MAX7357/MAX7358 family of devices

has selectable device addresses through three external

inputs. The slave address consists of 4 fixed bits

(A6–A3 set to 1110); followed by 3 pin-programmable

bits (A2, A1, A0), as shown in Figure 7. The addresses

A2, A1, and A0 can also be driven dynamically if

required, but the values must be stable when they are

expected in the address sequence.

RST/INT

BYTE1

FLUSH-OUT DATA

NOTE: THE FLUSH-OUT SEQUENCE RUNS AT AN SC_ FREQUENCY OF 40kHz.

THE HOST MAY COMMUNICATE AT UP TO 400kHz. THE TIMING SHOWN IS NOT TO SCALE.

BYTE4

SDA

SCL

SD_

SC_

Figure 6. Bus Lock-Up Detection, Isolation, and Notification Timing Diagram

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

12 ______________________________________________________________________________________

Available addresses depend on the hardware connec-

tions of pins A2, A1, and A0 as shown in Table 1.

The last bit following the slave address bit A0 on an I

command defines the operation to be performed. When

the last bit sets to logic 1, a read is selected while logic

0 selects a write operation.

The MAX7357 and MAX7358 have 7 registers (shown in

Table 2) that can be accessed through the I

C bus. The

MAX7357 powers up with all of these registers accessi-

ble. The initial register address counter is at 0x00. The

MAX7358 powers up in basic mode with only the switch

control register available. Writing to a MAX7358

changes only the contents of the switch control register.

By sending a unique I

C sequence to the MAX7358, all

7 registers become available.

Only the MAX7356 device address is required to gain

access to its registers. A typical I

C command to com-

municate with the MAX7356 starts with its device

address followed directly by data bytes.

A5 R/WA6 A4 A3 A2 A1 A0

FIXED

PIN-SELECTABLE BITS

Figure 7. MAX7356/MAX7357/MAX7358 Slave Address

CONNECTION

A6 A5 A4 A3 A2 A1 A0

GND GND GND 1110000

GND GND V

1110001

GND V

GND 1110010

GND V

1110011

GND GND 1110100

GND V

1110101

GND 1110110

1110111

Table 1. MAX7356/MAX7357/MAX7358 Switch Multiplexer Device Address

POR DEFAULT SETTING

NAME

B7 B6 B5 B4 B3 B2 B1 B0

ACCESS

Switch

Control

00000000 R/W

Table 3. MAX7357 and MAX7358 Basic-

Mode Register Map

POR DEFAULT SETTING

INTERNAL

ADDRESS

B7 B6 B5 B4 B3 B2 B1 B0

ADDRESS

ACCESS

Switch Control 0x00 0 0 0 0 0 0 0 0 0x01 R/W

Configuration 0x01 0 0 0 0 0 0 0 1 0x02 R/W

Flush-Out Sequence 0x02 1 1 1 1 1 1 1 1

0x00 (W)

0x03 (R)

R/W

Lock-Up Indication 0x03 0 0 0 0 0 0 0 0 0x04 R

0x04 0 0 0 0 0 0 0 0 0x05 R

Traffic Prior to Lock-Up

0x05 0 0 0 0 0 0 0 0 0x06 R

Stuck High Fault 0x06 0 0 0 0 0 0 0 0 0x00 R

Table 2. MAX7357/MAX7358 Enhanced-Mode Register Map

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

MAX7357EUG+

Mfr. #:

Buy MAX7357EUG+

Manufacturer:

Maxim Integrated

Description:

Multiplexer Switch ICs 1-to-8 I2C Bus Switch/MUX

Lifecycle:

New from this manufacturer.

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MAX7357EUG+

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