MAX7357EUG+ Datasheet MAX7357ETG+T, MAX7358ETG+, MAX7357EUG+ | P13-P15

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

______________________________________________________________________________________ 13

Only the switch control register can be accessed through

an I

C write or read command. All data bytes are for

the switch control register. The last data byte in an I

write command is retained by the switch control register.

(MAX7357/MAX7358)

Only the MAX7357 or MAX7358 I

C device address is

required to gain access to its registers. A typical I

command to communicate with the MAX7357 or

MAX7358 starts with its device address and is followed

directly by data bytes. Internal register addresses are

not used in an I

C write or read command.

For enhanced mode, all registers are accessed in

sequence starting with the switch control register and

follows the order defined by internal register addresses

as shown in Table 2. Internal register addresses are

0x00, 0x01, 0x02, 0x03, 0x04, 0x05, and 0x06 for

switch control, configuration, flush-out sequence, lock-

up indication, first and second bytes of the traffic prior

to lock-up, and preconnection fault registers, respec-

tively. When writing data to the register(s), addressing

starts with address 0x00 and goes one higher in each

subsequent byte and comes back to 0x00 again after

0x02 since the next four higher addressed registers are

read only. Read access also starts with the internal reg-

ister address 0x00 and goes one higher in each subse-

quent byte and comes back to 0x00 again after 0x06.

For basic mode, only the switch control register can be

accessed through an I

C write or read command. All

data bytes are for the switch control register. The last

data byte in an I

C write command is retained by the

switch control register. Incomplete bytes are ignored.

Switch Control Register

The switch control register (Figure 8) selects which

channels will be connected to the main I

C bus. This

bus. The POR value for the switch control register is

0x00—all switches disconnected.

A SC_/SD_ downstream pair, or channel, is selected by

the contents of the switch control register. All bits of the

control byte are used to determine which channel is to

B6 B0B7 B5 B4 B3 B2 B1

CHANNEL SELECTION BITS (READ/WRITE)

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

Figure 8. Switch Control Register

B7 B6 B5 B4 B3 B2 B1 B0 COMMAND

XXXXXXX 0Channel 0 disabled

XXXXXXX 1Channel 0 enabled

X X X X X X 0 X Channel 1 disabled

X X X X X X 1 X Channel 1 enabled

X X X X X 0 X X Channel 2 disabled

X X X X X 1 X X Channel 2 enabled

X X X X 0 X X X Channel 3 disabled

X X X X 1 X X X Channel 3 enabled

X X X 0 X X X X Channel 4 disabled

X X X 1 X X X X Channel 4 enabled

XX0XXXXXChannel 5 disabled

XX1XXXXXChannel 5 enabled

X0XXXXXXChannel 6 disabled

X1XXXXXXChannel 6 enabled

0XXXXXXXChannel 7 disabled

1XXXXXXXChannel 7 enabled

Table 4. Switch Control Register Channel Selection

X = Don’t care.

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

14 ______________________________________________________________________________________

B7 B6 B5 B4 B3 B2 B1 B0 COMMAND

XXXXXXX0Interrupt with RST/INT disabled

XXXXXXX1Interrupt with RST/INT enabled

XXXXXX0XFlush-out disabled

XXXXXX1XFlush-out enabled

XXXXX0XXRST/INT released after a register read

XXXXX1XXRST/INT released after 1.6 seconds

XXXX0XXX

The lock-up register shows the current

condition

XXXX1XXX

The lock-up register data is not cleared

until a read

X X X 0 X X X X Disconnect all channels on bus lock-up

X X X 1 X X X X Disconnect only the locked up bus

X X 0 X X X X X Bus lock-up detection enabled

X X 1 X X X X X Bus lock-up detection disabled

X0XXXXXXEnhanced mode

X1XXXXXXBasic mode enabled

0XXXXXXXPreconnect test is disabled

1XXXXXXXPreconnect test is enabled

Table 5. Configuration Register Definition

X = Don’t care.

be selected. More than one channel can be selected

simultaneously. When a channel is selected, the channel

becomes active immediately after a stop condition has

been placed on the I

C bus. This ensures that all

SC_/SD_ lines are in a HIGH state when the channel is

made active, so that no false conditions are generated at

the time of connection.

Configuration Register

(MAX7357/MAX7358)

B0 = RST/INT serves as an interrupt when a bus lock-

up condition is detected.

B1 = Flush-out sequence is sent automatically on locked-

up channels when a lock-up condition is detected.

B2 = When B0 = 1, release the RST/INT output after

asserting for 1.6 seconds.

B3 = Data in the lock-up indication register cleared only

after reading the register.

B4 = Connected channels remain connected on detec-

tion of lock-up if the lock-up condition is present only on

a channel that is not connected.

B5 = Disable bus lock-up detection.

B6 = Basic mode.

B7 = Enables the preconnection wiggle test for SC_

and SD_.

Flush-Out Sequence Register

(MAX7357/MAX7358)

A flush-out sequence can be sent to a particular auxil-

iary bus automatically after the identification of the lock-

up condition. The flush-out sequence consists of 18

SC_ clock cycles. An 8-bit sequence for the SD_ to fol-

low during the flush-out cycle can also be defined by

writing to the flush-out sequence register. By default,

the flush-out sequence register is all ones. The

MAX7357 or MAX7358 attempt to send the one-byte

sequence followed by an additional clock cycle (NACK)

two times sequentially, followed by a stop condition.

The effectiveness of sending the flush-out sequence

depends on the behavior of the locked-up device. For

an auxiliary bus with only slave devices, it is more likely

that the SCL line can still be driven by the MAX7357 or

MAX7358. In this case, a slave device may respond to

a particular flush-out sequence. After the release of the

SD_ line by a “stuck” device, the remaining sequence

on the SD_ line can be used to reset itself.

Bus Lock-Up Indication Register

(MAX7357/MAX7358)

The bus master can read the lock-up indication byte to

identify the stuck channels. A bit set to ”1” indicates

that the associated channel is stuck. The indication for

a given channel remains as long as the lock-up condi-

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

______________________________________________________________________________________ 15

tion exists on that channel. If the interrupt feature is

selected (B0 of the configuration register is 1), howev-

er, the interrupt signal, RST/INT, deasserts (goes to

high) once this bus lock-up indication register is read.

If desired, setting bit B3 of the configuration register to

1 can latch the lock-up data. When B3 is set, the lock-

up bits remain set (even if a channel becomes

“unstuck”) until the lock-up indication register is read

by the master. Lock-up conditions on unconnected aux-

iliary buses are also detected. When this happens, oper-

ation is the same as when lock-ups are detected on

connected buses, except that, if desired, bus connec-

tions may be maintained as long as any detected lock-

ups are present only on unconnected channels. This

option is selected using bit B4 of the configuration regis-

ter. (Figure 9)

Traffic Prior to Lock-Up Register

(MAX7357/MAX7358)

The I

C bus traffic information per SCL clock is moni-

tored and stored into the two-byte traffic prior to lock-up

are stored in this register. This I

C bus traffic informa-

tion is frozen upon a bus lock-up detection. A host can

read these two bytes of traffic information upon the

reception of an interrupt signal. The contents of the traf-

fic prior to lock-up register is released and refreshed

once it is read.

The traffic prior to lock-up register can be used to iden-

tify the device address as well as the following byte

involved in a bus lock-up.

When troubleshooting an I

C bus, a scope is usually

used to capture traffic leading to the problem. The con-

tents of the traffic prior to the bus fault can usually be

determined by identifying a device address, a register

address, or a part of this data.

Table 7 shows contents of the traffic prior to the lock-up

strated by Figure 10.

Figure 9. Lock-Up Indication Bits

B7 B6 B5 B4 B3 B2 B1 B0 COMMAND

XXXXXXX0Channel 0 no lock-up

XXXXXXX1Channel 0 lock-up

XXXXXX0XChannel 1 no lock-up

XXXXXX1XChannel 1 lock-up

X X X X X 0 X X Channel 2 no lock-up

X X X X X 1 X X Channel 2 lock-up

X X X X 0 X X X Channel 3 no lock-up

X X X X 1 X X X Channel 3 lock-up

X X X 0 X X X X Channel 4 no lock-up

X X X 1 X X X X Channel 4 lock-up

X X 0 X X X X X Channel 5 no lock-up

X X 1 X X X X X Channel 5 lock-up

X0XXXXXXChannel 6 no lock-up

X1XXXXXXChannel 6 lock-up

0XXXXXXXChannel 7 no lock-up

1XXXXXXXChannel 7 lock-up

Table 6. Lock-Up Register Channel Indication

X = Don’t care.

B6 B0B7 B5 B4 B3 B2 B1

CHANNEL LOCK-UP INDICATION BITS (READ)

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

MAX7357EUG+

Mfr. #:

Buy MAX7357EUG+

Manufacturer:

Maxim Integrated

Description:

Multiplexer Switch ICs 1-to-8 I2C Bus Switch/MUX

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MAX7357EUG+

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