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MAX7357EUG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX7356/MAX7357/MAX7358
1-to-8 I
2
C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3)
(V
DD
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Propagation Delay from SDA to
SD_ or SCL to SC_
t
PD
(Note 7) 0.3 ns
SCL Clock Frequency f
SCL
0 100 kHz
Bus Free Time Between a STOP
and START Condition
t
BUF
4.7 µs
Hold Time (Repeated) START
Condition After this Period, the
First Clock Pulse is Generated
t
HD
;
STA
4.0 µs
LOW Period of the SCL Clock t
LOW
4.7 µs
HIGH Period of the SCL Clock t
HIGH
4.0 µs
Setup Time for a Repeated
START Condition
t
SU;STA
4.7 µs
Setup Time for a STOP Condition t
SU
;
STO
4.0 µs
Data Hold Time t
HD
;
DAT
(Note 8) 0 3.45 µs
Data Setup Time t
SU
;
DAT
250 ns
Rise Time of Both SDA and SCL
Signals
t
R
1000 ns
Fall Time of Both SDA and SCL
Signals
t
F
300 ns
Capacitive Load for Each Bus
Line
C
b
400 pF
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
t
SP
50 ns
ELECTRICAL CHARACTERISTICS (5V SUPPLY) (continued)
(V
DD
= +4.5V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= +5V, T
A
= +25°C.) (Notes 2–5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capacitance C
I
V
I
= GND 2 pF
PASS GATE
Switch Resistance R
ON
V
DD
= 4.5V to 5.5V, V
O
= 0.4V, I
O
= 15mA 4 9 24 Ω
V
SWin
= V
DD
= 5.0V, I
SWout
= -100µA 3.6
Switch Output Voltage V
SW
V
S Wi n
= V
D D
= 4.5V to 5.5V , I
S Wo ut
= - 100µA 2.6 4.5
V
MAX7356 -1 +1
Leakage Current I
L
V
I
= V
DD
or GND
Enhanced mode
(MAX7357/MAX7358)
-2 +2
µA
Input/Output Capacitance C
IO
V
I
= GND 3 pF
OUTPUT RST/INT
Low-Level Output Current I
OL
V
OL
= 0.4V (MAX7357/MAX7358) 3 mA
Leakage Current I
LH
, I
LI
V
RST/INT
= V
DD
or GND -1 +1 µA
MAX7356/MAX7357/MAX7358
1-to-8 I
2
C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3) (continued)
(V
DD
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(High to low) 1
Data Valid Time t
VD
;
DAT
(Low to high) 0.6
µs
Data Valid Acknowledge t
VD:ACK
1µs
Low-Level Reset Time t
WL(rst)
5ns
Reset Time t
rst
500 ns
Recovery to Start t
REC
;
STA
0ns
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3)
(V
DD
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Propagation Delay from SDA to
SD_ or SCL to SC_
t
PD
(Note 7) 0.3 ns
SCL Clock Frequency f
SCL
0 400 kHz
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3 µs
Hold Time (Repeated) START
Condition After this Period,
the Fi r st C l ock P ul se i s Gener ated
t
HD
;
STA
0.6 µs
LOW Period of the SCL Clock t
LOW
1.3 µs
HIGH Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated
START Condition
t
SU;STA
0.6 µs
Setup Time for a STOP Condition t
SU
;
STO
0.6 µs
Data Hold Time t
HD
;
DAT
(Note 8) 0 0.9 µs
Data Setup Time t
SU
;
DAT
100 ns
Rise Time of Both SDA and SCL
Signals
t
R
20 +
0.1C
b
300 ns
Fall Time of Both SDA and SCL
Signals
t
F
20 +
0.1C
b
300 ns
Capacitive Load for Each Bus
Line
C
b
400 pF
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
t
SP
50 ns
(High to low) 1
Data Valid Time t
VD
;
DAT
(Low to high) 0.6
µs
Data Valid Acknowledge t
VD
;
ACK
1µs
Low-Level Reset Time t
WL(rst)
5ns
Reset Time t
rst
500 ns
Recovery to START t
REC
;
STA
0ns
MAX7356/MAX7357/MAX7358
1-to-8 I
2
C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3) (continued)
(V
DD
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
Note 2: All devices are 100% production tested at T
A
= +25°C. Specifications are over -40°C to +85°C and are guaranteed by
design.
Note 3: Subscript SW refers to all SC_ and SD_ pins.
Note 4: V
SWin
= Switch input voltage; I
SWout
= Current between SD_ and SDA or SC_ and SCL. See Figure 4.
Note 5: V
I
= V
SD_
or V
SC_
.
Note 6: All timing is measured using 20% and 80% levels, unless otherwise noted.
Note 7: Pass gate propagation delay is calculated from the 20Ω typical R
ON
and the 15pF load capacitance.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(min)
of the SCL signed)
to bridge the undefined region of the falling edge of SCL.
SDA
SCL
t
BUF
t
SU;STO
t
SP
t
HD;STA
t
SU;STA
t
F
t
HIGH
t
HD;DAT
t
R
t
LOW
t
HD;STA
SP
Sr
P
t
SU;DAT
Figure 1. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
RESET
t
REC;STA
t
WL(rst)
t
rst
Figure 2. RST Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX7357EUG+

Mfr. #:
Buy MAX7357EUG+
Manufacturer:
Maxim Integrated
Description:
Multiplexer Switch ICs 1-to-8 I2C Bus Switch/MUX
Lifecycle:
New from this manufacturer.
Delivery:
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