MAX7357EUG+ Datasheet MAX7357ETG+T, MAX7358ETG+, MAX7357EUG+ | P16-P18

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

16 ______________________________________________________________________________________

B7 B6 B5 B4 B3 B2 B1 B0 COMMAND

XXXXXXX0Channel 0 not stuck high

XXXXXXX1Channel 0 stuck high

XXXXXX0XChannel 1 not stuck high

XXXXXX1XChannel 1 stuck high

X X X X X 0 X X Channel 2 not stuck high

X X X X X 1 X X Channel 2 stuck high

X X X X 0 X X X Channel 3 not stuck high

X X X X 1 X X X Channel 3 stuck high

X X X 0 X X X X Channel 4 not stuck high

X X X 1 X X X X Channel 4 stuck high

X X 0 X X X X X Channel 5 not stuck high

X X 1 X X X X X Channel 5 stuck high

X0XXXXXXChannel 6 not stuck high

X1XXXXXXChannel 6 stuck high

0XXXXXXXChannel 7 not stuck high

1XXXXXXXChannel 7 stuck high

Table 8. Stuck HIGH Fault Register Channel Indication

X = Don’t care.

ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 NOTE

0x04 0 1 1 01000Write to the troubled device address

0x05 0 1 1 00000The first data byte with trailing 0’s due to lock-up

Table 7. A Traffic Prior to Lock-Up Register Contents Example

Stuck HIGH Fault Register

(MAX7357/MAX7358)

Following an interrupt when bit B0 and B7 are enabled,

the bus master can read the stuck high fault byte to

identify stuck channels. A bit set to ”1” indicates that

the associated channel is stuck, and will not be allowed

to be connected to the host bus. The stuck high fault

enabled, RST/INT deasserts (goes to high) once this

time a disconnected bus is selected for connection, the

preconnect test runs. If the fault still exists, the fault

handling sequence repeats and the faulty bus will not

be allowed to connect to the host bus.

RST

(MAX7356)

The RST on the MAX7356 can be used to reset the

MAX7356 by a host. The RST input is an active-low sig-

nal. By asserting this signal low for a minimum of t

WL(rst)

externally, the MAX7356 resets its I

C state machine

and deselects all channels. RST is overvoltage-tolerant

to +6V. The RST input must be connected to V

through a pullup resistor.

RST

INT

(MAX7357/MAX7358)

The RST/INT on the MAX7357 or MAX7358 is bidirec-

tional. It can be used to reset the device by a host or by

the device to send an interrupt signal to the host. The

RST/INT input is an active-low signal. By asserting

RST/INT low for a minimum of t

WL(rst)

externally, the

device resets its registers and I

C state machine and

deselects all channels. When RST/INT is configured to

notify the host of fault conditions, and while RST/INT

is being used as an output by the MAX7357 or

MAX7358 (sending an interrupt to the host), it does not

function as a reset input. RST/INT is overvoltage-tolerant

to +6V. RST/INT must be connected to V

through a

pullup resistor.

Interrupt Signal (MAX7357/MAX7358)

A bus lock-up-caused interrupt signal can be sent to a

host through the bidirectional RST/INT pin depending

on whether or not bit B0 of the configuration register is

set. Configuration register bit B2 controls how the inter-

rupt signal is reset. When B2 = 0, the interrupt signal

asserts (stays low) until the lock-up indication register is

read. When B2 = 1, the interrupt signal deasserts after

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

______________________________________________________________________________________ 17

2 seconds. The interrupt signal asserts again once a

new lock-up is detected. The interrupt signal does not

activate the reset function.

Serial Interface

Serial Addressing

The MAX7356/MAX7357/MAX7358 operate as a slave

that sends and receives data through an I

C interface.

The interface uses a serial-data line (SDA) and a serial-

clock line (SCL) to achieve bidirectional communication

between master(s) and slave(s). The master initiates all

data transfers to and from the MAX7357 or MAX7358

and generates the SCL clock that synchronizes the

data transfer.

SDA operates as both an input and an open-drain out-

put. A pullup resistor (4.7kΩ, typ) is required on SDA.

SCL operates only as an input. A pullup resistor (4.7kΩ,

typ) is required on SCL if there are multiple masters on

the 2-wire interface, or if the master in a single-master

system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7356/MAX7357/

MAX7358’s 7-bit slave address plus R/W bit, and then

optionally 1 or more data bytes, and finally a STOP con-

dition (Figure 10).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. The master signals the beginning of a trans-

mission with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 11).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 12).

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to handshake receipt of each byte of data (Figure

13). Each byte transferred effectively requires 9 bits.

The master generates the 9th clock pulse, and the

recipient pulls down SDA during the acknowledge

clock pulse, so the SDA line is stable low during the

high period of the clock pulse. When the master is

transmitting to the MAX7356/MAX7357/MAX7358, the

MAX7356/MAX7357/MAX7358 generate the acknowl-

START

0 A 01 0 01 1 0S 0 0 L L L L L L L L L L L L L L L1 1

ACKNOWLEDGE FROM

THE TROUBLED DEVICE

LOCK-UP

OCCURS

FIRST DATA BYTE SECOND DATA BYTE

Figure 10. Bus Lock-Up During a 3-Byte Write Command

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 11. Start and Stop Conditions

SDA

SCL

DATA STABLE

DATA VALID

CHANGE OF

DATA ALLOWED

Figure 12. Bit Transfer

CLOCK PULSE FOR

ACKNOWLEDGMENT

NOT ACKNOWLEDGE

ACKNOWLEDGE

12 8 9

SDA

SCL

START

CONDITION

Figure 13. Acknowledge

MAX7356/MAX7357/MAX7358

1-to-8 I

C Bus Switches/Multiplexers with Bus

Lock-Up Detection, Isolation, and Notification

18 ______________________________________________________________________________________

edge bit because the device is the recipient. When the

MAX7356/MAX7357/MAX7358 are transmitting to the

master, the master generates the acknowledge bit

because the master is the recipient.

Slave Address

The MAX7356/MAX7357/MAX7358 have 7-bit-long

slave addresses (Figure 6). The eighth bit following the

7-bit slave address is the R/W bit. It is low for a write

command, and high for a read command.

Accessing the MAX7356

A single-byte write to the MAX7356 sets the switch

control register.

A multibyte write to the MAX7356 writes repeatedly to

the switch control register. The last byte written deter-

mines the contents of the register.

A single-byte read from the MAX7356 returns the con-

tents of the switch control register.

A multibyte read (2 or more bytes before the I

C STOP

bit) from the MAX7356 returns the contents of the

switch control register repeatedly.

Accessing the MAX7357/MAX7358 in

Enhanced Mode

In enhanced mode, all 7 registers are enabled. These

registers are autoincremented starting with the switch

control register during each I

C transaction. When a

new transaction begins, the switch control register is

the first register accessed.

A single-byte write to the MAX7357 or MAX7358 sets

the switch control register.

A 2-byte write to the MAX7357 or MAX7358 sets the

switch control and configuration registers.

A 3-byte write to the MAX7357 or MAX7358 sets the

switch control, configuration, and flush-out sequence

registers.

A multibyte write to the MAX7357 or MAX7358 with

more than three bytes sets the first three registers, then

resets the pointer back to the switch control register

(0x00) since the remaining registers are read only.

Subsequent bytes of data, after 3 bytes, begin overwrit-

ing the first set of data starting with 0x00, 0x01, 0x02,

then looping back to 0x00 again, and continuing until a

STOP condition is received.

A single-byte read from the MAX7357 or MAX7358

returns the contents of the switch control register.

A multibyte read from the MAX7357 or MAX7358 returns

contents of all 7 registers in sequence and repeats.

The internal register address count always begins with

the switch control register, 0x00.

Accessing the MAX7357/MAX7358

in Basic Mode

In basic mode, only the switch control register is

enabled.

A single-byte write to the MAX7357 or MAX7358 sets

the switch control register.

A multibyte write to the MAX7357 or MAX7358 in basic

mode writes repeatedly to the switch control register.

The last byte written determines the contents of the reg-

ister.

A single-byte read from the MAX7357 or MAX7358

returns the contents of the switch control register.

A multibyte read (2 or more bytes before the I

C STOP

bit) from the MAX7357 or MAX7358 returns the contents

of the switch control register repeatedly.

Writing to the MAX7356

The MAX7356’s switch control register can be written by

an I

C write command starting with the device address

for the MAX7356 and followed by data bytes. The last

data byte is stored into the switch control register.

A write to the MAX7356 starts with the master transmitting

the slave address with the R/W bit set low. The MAX7356

acknowledges the slave address. The master can then

issue a STOP condition after the acknowledge (Figure 14),

but typically the master proceeds to transmit one or more

bytes of data. The MAX7356 acknowledges these subse-

quent bytes of data and updates the switch control regis-

ter when the master issues a STOP condition (Figure 14).

Writing to the MAX7357/MAX7358 in

Enhanced Mode

The MAX7357 and MAX7358 registers can be written

by an I

C write command starting with the device

address for the MAX7357 or MAX7358 and followed by

data bytes. The first data byte is stored into the switch

control register and subsequent data bytes are stored

into the subsequent registers.

A write to the MAX7357 or MAX7358 starts with the

master transmitting the slave address with the R/W bit

set low. The MAX7357 or MAX7358 acknowledge the

slave address. The master can then issue a STOP con-

dition after the acknowledge (Figure 15), but typically

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

MAX7357EUG+

Mfr. #:

Buy MAX7357EUG+

Manufacturer:

Maxim Integrated

Description:

Multiplexer Switch ICs 1-to-8 I2C Bus Switch/MUX

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