MAX7356/MAX7357/MAX7358
1-to-8 I
2
C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
______________________________________________________________________________________ 19
the master proceeds to transmit one or more bytes of
data. The MAX7357 or MAX7358 acknowledge these
subsequent bytes of data and update corresponding
registers with each new byte until the master issues a
STOP condition (Figure 15).
Writing to the MAX7357/MAX7358
in Basic Mode
The MAX7357 and MAX7358 switch control register can
be written by an I
2
C write command starting with the
device address for the MAX7357 or MAX7358 and fol-
lowed by data bytes. The last data byte is stored in the
switch control register.
A write to the MAX7357 or MAX7358 starts with the
master transmitting the slave address with the R/W bit
set low. The device acknowledges the slave address.
The master can then issue a STOP condition after the
acknowledge (Figure 16), but typically the master pro-
ceeds to transmit one or more bytes of data. The
MAX7357 or MAX7358 acknowledge these subsequent
bytes of data and update the switch control register
when the master issues a STOP condition (Figure 16).
Reading from the MAX7356
A read from the MAX7356 starts with the master trans-
mitting the slave address with the R/W bit set high. The
MAX7356 acknowledges the slave address. The master
can read 1 byte from the switch control register and
then issue a STOP condition (Figure 17). If the master
reads more than one byte, the master upon reception
acknowledges each byte. All bytes return the contents
of the switch control register.
Reading from the MAX7357/MAX7358
in Enhanced Mode
A read from the MAX7357 or MAX7358 starts with the
master transmitting the slave address with the R/W bit
set high. The device acknowledges the slave address.
The master can read 1 byte from the device and then
issue a STOP condition (Figure 18). In this case, the
device transmits the data byte from the switch control
register. Typically, the master reads 1 or 2 bytes with
each byte being acknowledged by the master upon
reception. The first data byte comes from the switch
control register and subsequent data bytes come from
the subsequent registers in order.
