LTC2946
12
2946fa
For more information www.linear.com/LTC2946
APPLICATIONS INFORMATION
is shown where the ADC periodically calibrates the cur-
rent sense amplifier with other voltages sequenced for
conversions in between.
Tw
o factors need to be considered when selecting between
these configurations:
1. Presence of load current harmonics in sync with the
windows when the ADC is not sampling the current.
The user can improve measurement accuracy of the
load current signal with such harmonics by selecting
a higher duty cycle for ΔSENSE. For most complete
coverage, the ADC can be configured to continuously
measure the current by setting CA[2:0] to 110.
2. Increasing the duty cycle for current measurement
will result in less frequent updates of the current
sense amplifier’s offset and the supply voltage values,
hence the amount they drift with respect to time and
temperature determines the best configuration to use.
An on-demand update can also be done with a single
I
2
C write transaction to the CTRLA register, which will
command new measurements of the current sense
amplifier’s offset and the supply voltage. The results
will be used for offset calibration and for providing the
voltage value for the multiplier. For example, if CA[6:5]
is set to code 11, and CA[2:0] is set to 110, a
new
offset
and voltage values will be produced two ADC
conversions after the I
2
C write transaction. The ADC
will continuously measure the current thereafter.
The timing diagram shown in Figure 2d illustrates the
sequence in which the power and accumulator data are
generated following conversions in the default configura
-
tion. At
t
1
, the ADC has just finished a conversion of the
current (ΔSENSE) signal. The time counter is incremented
by one count while the new current data at t
1
is added to
the charge accumulator. A new power value is generated
by multiplying I
(t1)
with the previous voltage (V
IN
) data
that is then added to the energy accumulator. From t
1
to
t
3
, the systematic offset of the current sense amplifier is
measured and stored. The ADC then performs a conversion
on V
IN
. A calibration is done again at t
4
before the ADC
converts ΔSENSE. The charge and energy accumulators
are incremented at t
2
, t
3
, t
4
, t
5
, t
6
and t
7
, with current and
power data from time t
1
. The timer counter will keep track
Data Converter, Multiplier and Accumulator
The LTC2946 features an onboard, 12-bit Δ∑ ADC that
inherently averages input signal
and noise over the con-
version time
window. The differential voltage between
SENSE
+
and SENSE
–
(ΔSENSE) is monitored with 25μV/
LSB resolution (102.4mV full-scale) to allow accurate
measurement of the load current across very low value
shunt resistors. The supply voltage at V
DD
or SENSE
+
is
directly measured with 25mV/LSB resolution (102.4V
full-scale). The voltage at the uncommitted ADIN pin can
also be measured with 0.5mV/LSB resolution (2.048V full-
scale) to allow monitoring of an arbitrary external voltage.
The supply voltage data is derived from V
DD
, SENSE
+
or
ADIN depending on the external application circuit. SENSE
+
is selected by default as it is normally connected to the
supply voltage as shown in Figure 4 (4a to 4c) and Figure
5b. In negative supply voltage systems, such as shown in
Figure 5d, V
DD
is used to measure the supply voltage at
GND with respect to the device ground. For positive and
negative supply voltages of more than 100V, as shown in
Figure 5a and Figure 5c, external resistors can be used to
divide down the voltage for ADIN to measure the supply
voltage. CA[4:3] in the CTRLA register select between V
DD
,
SENSE
+
and ADIN for supply voltage data. More details
can be found in Table 3. A 24-bit power value is generated
by digitally multiplying the 12-bit load current data with
the 12-bit supply voltage data. 1LSB of power is 1LSB of
voltage multiplied by 1LSB of ΔSENSE (current). The result
is held in the three adjacent POWER registers (Table 2).
During conversions, the data converter’s input is mul
-
tiplexed to measure four voltages: ΔSENSE, the current
sense
amplifier’s offset, V
DD
or V
SENSE
+
, and V
ADIN
at
various duty cycle by configuring CA[6:5] and CA[2:0]
in the CTRLA register (Table 3). Some configurations
are shown in Figure 2 (2a to 2c) to illustrate the various
conversion timing sequences. In Figure 2a, it is shown
that upon power-up or after an I
2
C write transaction to
the CTRLA register the ADC will first measure the current
sense amplifier’s offset (calibration) and again after every
other conversion which can be either V
ADIN
, the supply
voltage (V
DD
or V
SENSE
+
) or the load current (ΔSENSE).
Figure 2b shows periodic calibration performed every 16
conversions. In Figure 2c a more specific configuration
