LTC2946
32
2946fa
For more information www.linear.com/LTC2946
Table 11. FAULT2 Register (41h): Read/Write
BIT REGISTER NAME OPERATION DEFAULT
F2[7] Reserved 1
F2[6] GPIO1 Input Fault Indicates GPIO1 Was at Active Level as a General Purpose Input
[1] = GPIO1 Input Was Active
[0] = GPIO1 Input Was Inactive
0
F2[5] GPIO2 Input Fault Indicates GPIO2 Was at Active Level as a General Purpose Input
[1] = GPIO2 Input Was Active
[0] = GPIO2 Input Was Inactive
0
F2[4] GPIO3 Input Fault Indicates GPIO3 Was at Active Level as a General Purpose Input
[1] = GPIO3 Input Was Active
[0] = GPIO3 Input Was Inactive
0
F2[3] Stuck-Bus Timeout Wake-Up Fault With CB[4] = 1
[1] = Part Exited Shutdown Mode After Stuck-Bus Timer Expired
[0] = No Stuck Bus Timeout Wake-Up Fault Occurred
0
F2[2] Energy Register Overflow Fault Energy Register Overflow
[1] = Energy Register Overflow Fault
[0] = No Energy Overflow Fault
0
F2[1] Charge Register Overflow Fault Charge Register Overflow
[1] = Charge Register Overflow Fault
[0] = No Charge Overflow Fault
0
F2[0] Time Counter Register
Overflow Fault
Time Counter Register Over
flow
[1] = Time Counter Register Overflow Fault
[0] = No Time Counter Overflow Fault
0
Table 12. GPIO3_CTRL Register (42h): Read/Write
BIT REGISTER NAME OPERATION DEFAULT
GC[7] Alert Generated If GPIO3 is configured as ALERT output, it pulls low when alert is generated. Otherwise,
this bit does not have an effect on GPIO3. This bit is set when an alert is generated or a
1 is written. To clear this bit, write 0 via I
2
C.
0
GC[6] GPIO3 Pull-Down Control Controls GPIO3 as a General Purpose Output
[1] = GPIO3 Pulls Low
[0] = GPIO3 Hi-Z
This bit does not have effect on GPIO3 if it is configured otherwise.
0
GC[5:0] Reserved Read Only 00000b
Table 13. CLK_DIV Register (43h): Read/Write
BIT REGISTER NAME OPERATION DEFAULT
CD[7:5] Reserved Read Only 000b
CD[4:0] Clock Divider Integer Input clock frequency at CLKIN is divided by 4× of this integer to produce the target
250kHz system clock.
00100b
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