LTC2946
20
2946fa
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pointer automatically increments by 1 after each byte of
data is read or written. After the register address reaches
43h, it will roll over to 00h and continue incrementing. A
STOP condition resets the register address pointer to 00h.
The data formats for the above commands are shown in
Figure 7 through Figure 13. Note that only the read byte
command is available to the E7 and E8 (MFR_SPECIAL_ID)
registers (Table 2).
I
2
C Device Addressing
Nine distinct I
2
C bus addresses are configurable using the
three-state pins ADR0 and ADR1, as shown in Table 1.
ADR0 and ADR1 should be tied to INTV
CC
, to GND, or
left floating (NC) to configure the lower four address bits.
During low power shutdown, the address select state
is latched into memory powered from standby supply.
Address bits a6, a5 and a4 are permanently set to 110b
and the least significant bit is the R/W bit. In addition, all
LTC2946 devices will respond to a common mass write
address 1100_110b; this allows the bus master to write
to several LTC2946s simultaneously, regardless of their
individual address settings. The LTC2946 will also respond
to the standard ARA address 0001_100b if the
GPIO3
(ALER
T) pin is asserted. See the Alert Response Protocol
section for more details. The LTC2946 will not respond to
the ARA address if no alerts are pending.
START and STOP Conditions
When the I
2
C bus is idle, both SCL and SDA are in the HIGH
state. A bus master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL stays high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from LOW to high while SCL stays
high. The bus is then free for another transmission.
Stuck-Bus Reset
The LTC2946 I
2
C interface features a stuck-bus reset timer
to prevent it from holding the bus lines low indefinitely if
the SCL signal is interrupted during a transfer. The timer
starts when either SCL or SDAI is low, and resets when
both SCL and SDAI are pulled high. If either SCL or SDAI
are low for over 33ms, the stuck-bus timer will expire, and
the internal I
2
C interface and the SDAO pin pull-down logic
will be reset to release the bus. Normal communication
will resume at
the next START command.
Acknowledge
The
acknowledge signal is used for handshaking between
the master and the slave to indicate that the last byte of
data was received. The master always releases the SDA
line during the acknowledge clock pulse. The LTC2946 will
pull the SDA line low on the 9th clock cycle to acknowledge
receipt of the data. If the slave fails to acknowledge by
leaving SDA high, then the master can abort the transmis
-
sion by generating a STOP condition. When the master is
receiving data from the slave, the master must acknowledge
the slave by pulling down the SDA line during the 9th clock
pulse to indicate receipt of a data byte. After the last byte
has been received by the master, it will leave the SDA line
high (not acknowledge) and issue a STOP condition to
terminate the transmission.
Write Protocol
The master begins a write operation with a START condition
followed by the seven-bit slave address and the R/W bit
set to zero. After the addressed LTC2946 acknowledges
the address byte, the master then sends a command byte
that indicates which internal register the master wishes to
write. The LTC2946 acknowledges this and
then latches
the
lower six bits of the command byte into its internal
register address pointer. The master then delivers the
data byte and the LTC2946 acknowledges once more and
writes the data into the internal register pointed to by the
register address pointer. If the master continues sending
additional data bytes with a write word or extended write
command, the additional data bytes will be acknowledged
by the LTC2946, the register address pointer will auto
-
matically increment by one, and data will be written as
previously stated. The write operation terminates and the
register address pointer resets to 00h when the master
sends a STOP condition.
Read Protocol
The master begins a read operation with a START condi
-
tion followed by the 7-bit slave address and the R/W bit
set to zero. After the addressed LTC2946 acknowledges
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