LTC2946
14
2946fa
For more information www.linear.com/LTC2946
Since the accumulators contain multiple bytes of data,
a single page read transaction of the accumulators is
required to ensure the data is coherent. All the accumula
-
tors are writable, allowing them to be preloaded with given
values. The LTC2946 can then be configured to generate
an overflow alert after a specified amount of energy or
charge has been delivered or when a preset amount of
time has elapsed.
A snapshot mode is also included which makes a measure
-
ment of a single selected voltage (either ΔSENSE, V
DD
or
V
SENSE
+
, or V
ADIN
). To make a snapshot measurement,
write the 2-bit code of the desired ADC channel to CA[4:3]
and code 111 to CA[2:0] using a write byte command to
the CTRLA register. When the write byte command is
completed, the ADC converts the selected voltage and
the busy bit S2[3] in the STATUS2 register (see Table 10)
will be set to indicate that the conversion is in progress.
After completing the conversion, the ADC will halt and the
busy bit will reset to indicate that the data is ready. An
alert may be generated at the end of a snapshot conver
-
sion by setting bit AL2[7] in the ALERT2 register (
Table
8). To make another snapshot measurement, rewrite the
CTRLA register. In snapshot mode, the POWER registers,
time counters, charge and energy accumulators are not
refreshed.
Crystal Oscillator/External Clock
Accurately measuring energy/charge by integrating power/
current requires a precise integration period. The on-chip
clock of the LTC2946 is trimmed to within ±5%. To enable
timekeeping with the on-chip clock, tie CLKIN to GND and
leave CLKOUT open. For better accuracy, a crystal oscillator
or resonator may be connected to the CLKIN and CLKOUT
pins, as shown in Figure 1. Alternately, an external clock
between 1MHz and 25MHz may be applied to CLKIN with
CLKOUT left unconnected. The clock frequency at CLKIN is
divided by 4× the value in the CLK_DIV register (see Table
13) to generate an internal clock with targeted frequency
of 250kHz for the data converter’s delta-sigma modulator.
With an external clock or crystal, the sampling frequency
of the ADC can be adjusted by configuring the CLK_DIV
register (Register 43h). Limit the sampling clock to between
100kHz and 400kHz and at least 20kHz above or below f
IN
.
The delta-sigma ADC provides inherent averaging of the
input signal such that an
anti-aliasing filter is not required
in
most applications. However, noise ripple (f
IN
) occurring
at integer multiples of the modulator sampling frequency
(f
S
) can still pose problems. Figure 3 shows how the
sampling frequency as a function of the input frequency
affects the amount of error. When f
S
= f
IN
, in the worst
case the input signal may be sampled entirely at its peak
APPLICATIONS INFORMATION
Figure 3. Waveforms Showing the Effect of Aliasing
0µs 10µs 20µs 30µs 40µs 50µs 60µs 70µs 80µs 100µs90µs
2946 F03
f
S
= 0.9 • f
IN
t
IN
f
S
= 1.1 • f
IN
f
S
= f
IN
t
S
t
IN
t
S
t
IN
t
S
