APDS-9300-020 Datasheet APDS-9300-020 | P10-P12

Command Register

The command register species the address of the target register for subsequent read and write operations. The Send

Byte protocol is used to congure the COMMAND register. The command register contains eight bits as described in

Table 3. The command register defaults to 00h at power on.

Table 3. Command Register

ADDRESSCLEARCMD WORD Resv

67 5 4 23 1 0

00 0 0 00 0 0Reset Value:

COMMAND

Field BIT Description

CMD 7 Select command register. Must write as 1.

CLEAR 6 Interrupt clear. Clears any pending interrupt.

This bit is a write–one–to–clear bit. It is self clearing.

WORD 5 I

C Write/Read Word Protocol.

1 indicates that this I

C transaction is using either the I

C Write Word or Read Word protocol.

Resv 4 Reserved. Write as 0.

ADDRESS 3:0 Register Address.

This eld selects the specic control or status register for following write and read com-

mands according to Table 2.

POWERResvResv ResvResv Resv Resv

67 5 4 23 1 0

00 0 0 00 0 0Reset Value:

CONTROL

Control Register (0h)

The CONTROL register contains two bits and is primarily used to power the APDS-9300 device up and down as shown

in Table 4.

Table 4. Control Register

Field BIT Description

Resv 7:2 Reserved. Write as 0.

POWER 1:0 Power up/power down. By writing a 03h to this register, the device is powered up.

By writing a 00h to this register, the device is powered down.

NOTE: If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be used to verify that the device is communicating

properly.

Timing Register (1h)

The TIMING register controls both the integration time and the gain of the ADC channels. A common set of control bits

is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.

Table 5. Timing Register

Field BIT Description

Resv 7-5 Reserved. Write as 0.

GAIN 4 Switches gain between low gain and high gain modes.

Writing a 0 selects low gain (1x);

Writing a 1 selects high gain (16x).

MANUAL 3 Manual timing control.

Writing a 1 begins an integration cycle.

Writing a 0 stops an integration cycle.

NOTE: This eld only has meaning when INTEG = 11.

It is ignored at all other times.

Resv 2 Reserved. Write as 0.

INTEG 1:0 Integrate time. This eld selects the integration time for each conversion.

Integration time is dependent on the INTEG FIELD VALUE and the internal clock frequency. Nominal integration times

and respective scaling between integration times scale proportionally as shown in Table 6. See Note 5 and Note 6 on

page 4 for detailed information regarding how the scale values were obtained.

Table 6. Integration Time

Integ Field Value Scale Nominal Integration Time

00 0.034 13.7 ms

01 0.252 101 ms

10 1 402 ms

11 -- N/A

The manual timing control feature is used to manually start and stop the integration time period. If a particular integra-

tion time period is required that is not listed in Table 6, then this feature can be used. For example, the manual timing

control can be used to synchronize the APDS-9300 device with an external light source (e.g. LED). A start command to

begin integration can be initiated by writing a 1 to this bit eld. Correspondingly, the integration can be stopped by

simply writing a 0 to the same bit eld.

INTEGMANUALResvResv GAIN ResvResv

67 5 4 23 1 0

00 0 0 00 1 0Reset Value:

TIMING

Interrupt Threshold Register (2h - 5h)

The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison func-

tion for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low threshold specied,

an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses above the high threshold speci-

ed, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW and THRESHLOWHIGH provide the low byte

and high byte, respectively, of the lower interrupt threshold. Registers THRESHHIGHLOW and THRESHHIGHHIGH provide

the low and high bytes, respectively, of the upper interrupt threshold. The high and low bytes from each set of registers

are combined to form a 16–bit threshold value. The interrupt threshold registers default to 00h on power up.

Table 7. Interrupt Threshold Register

THRESHLOWLOW 2h 7:0 ADC channel 0 lower byte of the low threshold

THRESHLOWHIGH 3h 7:0 ADC channel 0 upper byte of the low threshold

THRESHHIGHLOW 4h 7:0 ADC channel 0 lower byte of the high threshold

THRESHHIGHHIGH 5h 7:0 ADC channel 0 upper byte of the high threshold

NOTE: Since two 8–bit values are combined for a single 16–bit value for each of the high and low interrupt thresholds, the Send Byte protocol

should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the

COMMAND eld and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired. The Write

Word protocol should be used to write byte–paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH registers (as well as the

THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16–bit ADC value in a single transaction.

Interrupt Control Register (6h)

The INTERRUPT register controls the extensive interrupt capabilities of the APDS-9300. The APDS-9300 permits tradi-

tional level–style interrupts. The interrupt persist bit eld (PERSIST) provides control over when interrupts occur. A value

of 0 causes an interrupt to occur after every integration cycle regardless of the threshold settings. A value of 1 results

in an interrupt after one integration time period outside the threshold window. A value of N (where N is 2 through15)

results in an interrupt only if the value remains outside the threshold window for N consecutive integration cycles. For

example, if N is equal to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds.

When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside of

the programmed threshold window. The interrupt is active–low and remains asserted until cleared by writing the COM-

MAND register with the CLEAR bit set.

NOTE: Interrupts are based on the value of Channel 0 only.

Table 8. Interrupt Control Register

PERSISTResvResv INTR

67 5 4 23 1 0

00 0 0 00 0 0Reset Value:

INTERRUPT

Field Bits Description

Resv 7:6 Reserved. Write as 0.

INTR 5:4 INTR Control Select. This eld determines mode of interrupt logic according to Table 9,

below.

PERSIST 3:0 Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10,

below.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

APDS-9300-020

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Manufacturer:

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Ambient Light Sensors ALPS Light Sensor

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