APDS-9300-020 Datasheet APDS-9300-020 | P13-P15

Table 9. Interrupt Control Select

Intr Field Value Read Value

00 Interrupt output disabled

01 Level Interrupt

Table 10. Interrupt Persistence Select

Persist Field Value Interrupt Persist Function

0000 Every ADC cycle generates interrupt

0001 Any value outside of threshold range

0010 2 integration time periods out of range

0011 3 integration time periods out of range

0100 4 integration time periods out of range

0101 5 integration time periods out of range

0110 6 integration time periods out of range

0111 7 integration time periods out of range

1000 8 integration time periods out of range

1001 9 integration time periods out of range

1010 10 integration time periods out of range

1011 11 integration time periods out of range

1100 12 integration time periods out of range

1101 13 integration time periods out of range

1110 14 integration time periods out of range

1111 15 integration time periods out of range

ID Register (Ah)

The ID register provides the value for both the part number and silicon revision number for that part number. It is a

read–only register, whose value never changes.

Table 11. ID Register

REVNOPARTNO

67 5 4 23 1 0

-- - - -- - -Reset Value:

Field Bits Description

PARTNO 7:4 Part Number Identication

REVNO 3:0 Revision number identication

ADC Channel Data Registers (Ch - Fh)

The ADC channel data are expressed as 16–bit values spread across two registers. The ADC channel 0 data registers,

DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 0. Registers

DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 1. All channel

data registers are read–only and default to 00h on power up.

Table 12. ADC Channel Data Registers

DATA0LOW Ch 7:0 ADC channel 0 lower byte

DATA0HIGH Dh 7:0 ADC channel 0 upper byte

DATA1LOW Eh 7:0 ADC channel 1 lower byte

DATA1HIGH Fh 7:0 ADC channel 1 upper byte

The upper byte data registers can only be read following a read to the corresponding lower byte register. When the

lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a subsequent read

to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between

the reading of the lower and upper registers.

NOTE: The Read Word protocol can be used to read byte–paired registers. For example, the DATA0LOW and DATA0HIGH registers

(as well as the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16–bit ADC value in a single transaction

Notes:

1. All linear dimensions are in millimeters

PCB Pad Layout

The suggested PCB layout is given below:

Notes:

1. All dimensions are in millimeters. Dimension tolerance is ±0.2 mm unless otherwise stated

APDS-9300 PACKAGE OUTLINE

Pin 1 : V

Pin 2 : GND

Pin 3 : ADDR SEL

Pin 4 : SCL

Pin 5 : SDA

Pin 6 : INT

UNIT: mm

Tolerance: +/- 0.2mm

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

APDS-9300-020

Mfr. #:

Buy APDS-9300-020

Manufacturer:

Broadcom / Avago

Description:

Ambient Light Sensors ALPS Light Sensor

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New from this manufacturer.

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APDS-9300-020