APDS-9300-020 Datasheet APDS-9300-020 | P7-P9

Typical Characteristics

Figure 4. Normalized Responsivity vs. Spectral Responsivity Figure 5. Normalized Responsivity vs. Angular Displacement * CL Package

SPECTRAL RESPONSIVITY

400

0.2

0.4

0.6

0.8

500 600 700 800 900 1000 1100

NORMALIZED RESPONSIVITY

300

CHANNEL 1

PHOTODIODE

CHANNEL 0

PHOTODIODE

- WAVELENGTH - nm

470 pF

ANGULAR DISPLACEMENT - °

NORMALIZED RESPONSIVITY

0.2

0.4

0.6

0.8

1.0

-90 -60 -30 0 30 60

OPTICAL AXIS

Principles of Operation

Analog–to–Digital Converter

The APDS-9300 contains two integrating analog–to–digi-

tal converters (ADC) that integrate the currents from the

channel 0 and channel 1 photodiodes. Integration of both

channels occurs simultaneously, and upon completion of

the conversion cycle the conversion result is transferred to

the channel 0 and channel 1 data registers, respectively.

The transfers are double buered to ensure that invalid

data is not read during the transfer. After the transfer, the

device automatically begins the next integration cycle.

Digital Interface

Interface and control of the APDS-9300 is accomplished

through a two–wire serial interface to a set of registers

that provide access to device control functions and out-

put data. The serial interface is compatible to I

C bus Fast–

Mode. The APDS-9300 oers three slave addresses that

are selectable via an external pin (ADDR SEL). The slave

address options are shown in Table 1.

Table 1. Slave Address Selection

ADDR SEL Terminal Level Slave Address

GND 0101001

Float 0111001

1001001

NOTE:

The Slave Addresses are 7 bits and please note the I

C protocols. A read/

write bit should be appended to the slave address by the master device

to properly communicate with the APDS-9300 device.

C Protocols

Each Send and Write protocol is, essentially, a series of

bytes. A byte sent to the APDS-9300 with the most sig-

nicant bit (MSB) equal to 1 will be interpreted as a COM-

MAND byte. The lower four bits of the COMMAND byte

form the register select address (see Table 2), which is

used to select the destination for the subsequent byte(s)

received. The APDS-9300 responds to any Receive Byte re-

quests with the contents of the register specied by the

stored register select address.

The APDS-9300 implements the following protocols of

the Philips Semiconductor I

C specication:

• I

C Write Protocol

• I

C Read Protocol

For a complete description of I

C protocols, please review

the I

C Specication athttp://www.semiconductors.phil-

ips.com

Figure 6. I

C Packet Protocol Element Key

Figure 7. I

C Write Protocols

Figure 8. I

C Read (Combined Format) Protocols

71 81 1 1 1

Data ByteSlave AddressS A PA

X X

A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)

P Stop Condition

Rd Read (bit value of 1)

S Start Condition

Sr Repeated Start Condition

Wr Write (bit value of 0)

X Shown under a field indicates that that field is required to have a value of X

... Continuation of protocol

Master –to–Slave

Slave –to–Master

81 81 1 1 17

Slave AddressS A

Command Code Data Byte A

71 81 1 1 81 17 1 1

Data Byte

Slave AddressS A

Command Code Slave Address

ASr Rd

Figure 9. I

C Write Word Protocols

Figure 10. I

C Read Word Protocols

81 81 1 1 8 17 1

Data Byte High

Slave Address

Command Code

Data Byte Low

71 81 1 1 17 1 1

Slave Address

Command Code

Slave Address

8 1

Data Byte Low

…

8 1

Data Byte High

The APDS-9300 is controlled and monitored by sixteen registers (three are reserved) and a command register accessed

through the serial interface. These registers provide for a variety of control functions and can be read to determine re-

sults of the ADC conversions. The register set is summarized in Table 2.

Table 2. Register Address

Address Register Name Register Function

-- COMMAND Species register address

0h CONTROL Control of basic functions

1h TIMING Integration time/gain control

2h THRESHLOWLOW Low byte of low interrupt threshold

3h THRESHLOWHIGH High byte of low interrupt threshold

4h THRESHHIGHLOW Low byte of high interrupt threshold

5h THRESHHIGHHIGH High byte of high interrupt threshold

6h INTERRUPT Interrupt control

7h -- Reserved

8h CRC Factory test — not a user register

9h -- Reserved

Ah ID Part number/ Rev ID

Bh -- Reserved

Ch DATA0LOW Low byte of ADC channel 0

Dh DATA0HIGH High byte of ADC channel 0

Eh DATA1LOW Low byte of ADC channel 1

Fh DATA1HIGH High byte of ADC channel 1

The mechanics of accessing a specic register depends on the specic I

C protocol used. Refer to the section on I

protocols. In general, the COMMAND register is written rst to specify the specic control/status register for following

read/write operations.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

APDS-9300-020

Mfr. #:

Buy APDS-9300-020

Manufacturer:

Broadcom / Avago

Description:

Ambient Light Sensors ALPS Light Sensor

Lifecycle:

New from this manufacturer.

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APDS-9300-020