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ZL30110LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006-2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
16.384 MHz
• Provides a range of output clocks:
• 65.536 MHz TDM clock locked to the input
reference
• General purpose 25 MHz fan-out to 6 outputs
locked to the external crystal or oscillator
• General purpose 125 MHz and 66 MHz or
100 MHz locked to the external crystal or
oscillator
• Provides DPLL lock and reference fail indication
• Automatic free run mode on reference fail
• DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
• Less than 5 psec
rms
on 25 MHz outputs, and less
than 0.6 ns
pp intrinsic jitter on the all other outputs
• Minimal input to output and output to output skew
• 25 MHz external master clock source: clock
oscillator or crystal
• Simple hardware control interface
Applications
• Clock rate conversion PLL for Telecommunication
Equipment
• Small/Medium Enterprise Router / Gateway
• Broadband access (xPON/xDSL) CPE gateway
Description
The ZL30110 clock rate conversion digital phase-
locked loop (DPLL) provides accurate and reliable
frequency conversion.
The ZL30110 generates a range of clocks that are
either locked to the input reference or locked to the
external crystal or oscillator.
In the locked mode, the reference input is continuously
monitored for a failure condition. In the event of a
failure, the DPLL continues to provide a stable free
running clock ensuring system reliability.
May 2009
Ordering Information
ZL30110LDE 32 Pin QFN Tubes, Bake & Dry Pack
ZL30110LDG1 32 Pin QFN* Trays, Bake & Dry Pack
ZL30110LDF1 32 Pin QFN* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
ZL30110
Telecom Rate Conversion DPLL
Data Sheet
Figure 1 - Functional Block Diagram
RST
OSCo
OSCi
REF
LOCK
APLL
C65o
REF_FAIL
C100/66o
DPLL
6 X C25o
APLL
C125o
OUT_SEL
State Machine
Reference
Master
Clock
Frequency
Synthesizer
Select MUX
Monitor
ZL30110 Data Sheet
2
Zarlink Semiconductor Inc.
1.0 Change Summary
The following table captures the changes from the April 2008 issue.
The following table captures the changes from the November 2006 issue.
2.0 Physical Description
2.1 Pin Connections
Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN with E-pad)
Page Item Change
1 Ordering Information Updates to Packaging Information. Added new
packaging variants. Added Section 8.0.
Page Item Change
19 “Performance Characteristics*
- Unfiltered Jitter Generation -
Pk-Pk“
Made an addition to the table.
ZL30110
26
28
30
32
12
10
8
64
2
14
16
18
2224 20
GND (33- E-pad)
C25co C25do C25eo AV
DD
C25fo C65o AV
DD
AV
CORE
V
CORE
LOCK
REF_FAIL
GND GNDV
CORE
V
CORE
GND
C125o
C100/66o
V
DD
OUT_SEL
V
DD
OSCi
OSCo
RST
C25bo
C25ao
GND
REF
IC
V
DD
GND
IC
ZL30110 Data Sheet
Table of Contents
3
Zarlink Semiconductor Inc.
1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 APLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.0 DPLL Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.0 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ZL30110LDG1

Mfr. #:
Buy ZL30110LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free Telecom Rate Conversion DPLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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