ZL30110 Data Sheet
9
Zarlink Semiconductor Inc.
3.2 Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30110 consists of a phase detector, a loop filter and a digitally controlled oscillator.
Phase Detector - the phase detector compares the input reference signal to the feedback signal and provides an
error signal corresponding to the phase difference between the two.
Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 922 Hz. For stability reasons,
the loop filter bandwidth for an 8 kHz reference is limited to a maximum of 58 Hz.
Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the ZL30110.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 25 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL goes into FreeRun mode, the LOCK pin will
initially stay high for 0.1 s. If at that point the DPLL is still in FreeRun mode, the LOCK pin will go low. In Freerun
mode the LOCK pin will go low immediately.
3.3 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizer to generate the output clock which is synchronized to
the inputs (REF). The frequency synthesizer uses digital techniques to generate output clock and advanced noise
shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability
and should be buffered when driving high capacitance loads.
3.4 State Machine
As shown in Figure 1, the state machine controls the DPLL.
3.5 APLL
The ZL30110 employ two Analog PLLs as a clock multiplying and rate conversion engine. One APLL is used to
multiply the master clock (OSCi) to 125 MHz, a second APLL is used to convert the master clock (OSCi) to
100 MHz or 66 MHz clock.
3.6 Master Clock
The ZL30110 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
