ZL30110LDG1 Datasheet ZL30110LDG1, ZL30110LDF1 | P10-P12

ZL30110 Data Sheet

Zarlink Semiconductor Inc.

4.0 DPLL Modes of Operation

The ZL30110 has two possible modes of operation; Normal, and Freerun. The ZL30110 starts up in Freerun mode,

it automatically transitions to Normal mode if a valid reference is available and transitions to Freerun mode if the

reference fails.

4.1 Freerun Mode

Freerun mode is typically used when an independent clock source is required or immediately following system

power-up before synchronization is achieved.

In Freerun mode, the ZL30110 provides timing and synchronization signals which are based on the master clock

frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals.

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a

±32 ppm output clock

is required, the master clock must also be

±32 ppm. See Applications - Section 6.2, “Master Clock“.

Freerun Mode is also used for short durations while system synchronization is temporarily disrupted. The accuracy

of the output clock during these input reference disruptions is better than the accuracy of the master clock (OSCi),

but it is off compared to the reference before disruptions.

4.2 Normal Mode

Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal

mode, the ZL30110 provides timing synchronization signals, which are synchronized to the input (REF). The input

reference signal may have a nominal frequency of 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of

the reference inputs are automatically detected by the reference monitors.

When the ZL30110 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy

of its freerunning local oscillator (see Figure 4). If the ZL30110 determines that its selected reference is disrupted

(see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted. If the ZL30110

determines that the reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover

from Freerun and transition to Normal mode.

When the ZL30110 is operating in Normal mode, if it determines that the input reference is disrupted (Figure 3) then

its state machine will cause it to automatically go to Freerun mode. When the ZL30110 determines that its selected

reference is not disrupted then the state machine will cause the DPLL to recover from Freerun and transition to

Normal mode.

Figure 4 - DPLL Mode Switching

Freerun

REF_FAIL=0

REF_FAIL=1

RST

Normal

ZL30110 Data Sheet

Zarlink Semiconductor Inc.

5.0 Measures of Performance

The following are some PLL performance indicators and their corresponding definitions.

5.1 Jitter

Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander

is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low

frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or

20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter

numbers, not cycle-to-cycle jitter.

5.2 Jitter Generation (Intrinsic Jitter)

Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually

measured with various band limiting filters depending on the applicable standards.

5.3 Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

5.4 Lock Time

This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and

output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).

Lock time is affected by many factors which include:

• initial input to output phase difference

• initial input to output frequency difference

• PLL loop filter bandwidth

The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output

to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and

frequency.

ZL30110 Data Sheet

Zarlink Semiconductor Inc.

6.0 Applications

This section contains ZL30110 application specific details for power supply decoupling, reset operation, clock and

crystal operation.

6.1 Power Supply Decoupling

Jitter levels on the ZL30110 output clocks may increase if the device is exposed to excessive noise on its power

pins. For optimal jitter performance, the ZL30110 device should be isolated from noise on power planes connected

to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note

ZLAN-178.

6.2 Master Clock

The ZL30110 can use either a clock or crystal as the master timing source.

6.2.1 Clock Oscillator

When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,

frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.

The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30110, and the OSCo

output should be left open as shown in Figure 5.

Figure 5 - Clock Oscillator Circuit

1 Frequency 25 MHz

2 Tolerance as required (better than +/-50ppm)

3 Rise & fall time < 8 ns

4 Duty cycle 40% to 60%

Table 1 - Clock Oscillator Specification

+3.3 V

25 MHz OUT

GND 0.1 µF

+3.3 V

OSCo

ZL30110

OSCi

No Connection

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