7
LTC3776
3776fa
FU CTIO AL DIAGRA
U
U
W
–
+
–
+
–
+
SHDN
0.6V
V
REF
EXTSS
0.7μA
CLK1
CLK2
0.54V
0.9 • V
REF
/2
V
FB1
V
FB2
SLOPE1
SLOPE2
RUN/SS
V
IN
C
VIN
V
IN
(TO CONTROLLER 1, 2)
R
VIN
SYNC/SSEN
PLLLPF
UNDERVOLTAGE
LOCKOUT
SYNC DETECT/
SPREAD
SPECTRUM
ENABLE
VOLTAGE
CONTROLLED
OSCILLATOR
SLOPE
COMP
VOLTAGE
REFERENCE
t
SEC
= 1ms
INTSS
PHASE
DETECTOR
IPROG1
IPROG2
IPRG1
IPRG2
VOLTAGE
CONTROLLED
OSCILLATOR
MAXIMUM
SENSE VOLTAGE
SELECT
PGOOD
SHDN
OV1
UV1
UV2
OV2
3776 FD
(Common Circuitry)
using the phase-locked loop, apply a CMOS compatible
clock with a frequency between 250kHz and 850kHz to this
pin. Tie this pin to GND to enable constant frequency
operation (300kHz, 550kHz or 750kHz as determined by the
state of the PLLLPF pin). Tie this pin to V
IN
to enable spread
spectrum operation. In spread spectrum mode, the
LTC3776’s frequency is randomly varied between 450kHz
and 580kHz.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE
+
.
SENSE1
+
/SENSE2
+
(Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connec-
tion to Inductor. Also the negative input to differential peak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the exter-
nal P-channel MOSFETs, the drain of the external N-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These pins
select the maximum allowed voltage drop between the
SENSE
+
and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to V
IN
, GND or float to select one of three discrete
levels.
V
FB1
/V
FB2
(Pins 24, 7/Pins 3, 10): Feedback Pins. Receives
the remotely sensed feedback voltage for its controller.
Exposed Pad (Pin 25/NA): The Exposed Pad (UF Package)
must be soldered to the PCB ground.
UU
U
PI FU CTIO S
(UF/GN Package)
