PCA9535_PCA9535C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 7 November 2017 10 of 34
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9535/PCA9535C by sending the device address and
setting the least significant bit to a logic 0 (see Figure 6 “
PCA9535; PCA9535C device
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9535/PCA9535C are configured to operate as four
register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and
Configuration Ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 8
and Figure 9). For example, if the first byte is
sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
At power-on reset, all registers return to default values.
(1) PCA9535C I/Os are open-drain only. The portion of the PCA9535 schematic marked inside the
dotted line box is not in PCA9535C.
Fig 7. Simplified schematic of I/Os
V
DD
I/O pin
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aac218
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
(1)
