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CS5464-IS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
CS5464
28 DS682F3
8. REGISTER DESCRIPTIONS
1. “Default” = bit states after power-on or reset
2. DO NOT write a “1” to any unpublished register bit.
3. DO NOT write to any unpublished register address.
8.1 Page Register
8.1.1 Page – Address: 31, Write-only, can be written from ANY page.
Default = 0
Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5464 is
12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The
Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages
are used,
Page is a write-only integer containing 7 bits.
8.2 Page 0 Registers
8.2.1 Configuration (Config) – Address: 0
Default = 1 (K=1)
PC[7:0] Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is signed
and in the range of -1.0
value 1.0 sample (OWR) intervals.
EWA Allows the E1
and E2 pins to be configured as open-drain outputs.
0 = Normal Outputs
1 = Open-drain Outputs
IMODE, IINV Interrupt configuration. Selects INT
pin behavior.
00 = Low Logic Level When Asserted
01 = High Logic Level When Asserted
10 = Low-going Pulse on New Interrupt
11 = High-going Pulse on New Interrupt
iCPU Inverts the CPUCLK output.
0=Default
1 = Invert CPUCLK.
K[3:0] Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K is
unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1.
MSB LSB
2
6
2
5
2
4
2
3
2
2
2
1
2
0
23 22 21 20 19 18 17 16
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
15 14 13 12 11 10 9 8
EWA - - IMODE IINV - - -
76543210
- - -iCPUK3K2K1K0
CS5464
DS682F3 29
8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2)
Address: 1 (I1), 2 (V1), 3 (P2), 7 (I2), 8 (V2), 9 (P2)
I1 (I2) and V1 (V2) contain instantaneous current and voltage, respectively, which are multiplied to yield in-
stantaneous power,
P1 (P2). These are two's complement values in the range of -1.0 value 1.0, with the
binary point to the right of the MSB.
8.2.3 Active Power (P1
AVG
, P2
AVG
)
Address: 4 (P1
AVG
), 10 (P2
AVG
)
Instantaneous power is averaged over each low-rate interval (
N samples) to compute active power, P1
AVG
(
P2
AVG
). These are two's complement values in the range of -1.0 value 1.0, with the binary point to the
right of the MSB.
8.2.4 RMS Current (I1
RMS
, I2
RMS
) and Voltage (V1
RMS
, V2
RMS
)
Address: 5 (I1
RMS
), 6 (V1
RMS
), 11 (I2
RMS
), 12 (V2
RMS
)
I1
RMS
(I2
RMS
) and V1
RMS
(V2
RMS
) contain the root mean square (RMS) values of I1 (I2) and V1 (V2), calcu-
lated each low-rate interval. These are unsigned values in the range of 0
value 1.0, with the binary point
to the left of the MSB.
8.2.5 Instantaneous Quadrature Power (Q1, Q2)
Address: 14 (Q1), 17 (Q2)
Instantaneous quadrature power,
Q1 (Q2), the product of voltage1 (voltage2) shifted 90 degrees and current1
(current2). These are two's complement values in the range of -1.0
value 1.0, with the binary point to the
right of the MSB.
8.2.6 Reactive Power (Q1
AVG
, Q2
AVG
)
Address: 13 (Q1
AVG
), 16 (Q2
AVG
)
Reactive power
Q1
AVG
(Q2
AVG
) is Q1 (Q2) averaged over every N samples. These are two's complement
values in the range of -1.0
value 1.0, with the binary point to the right of the MSB.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
.....
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
CS5464
30 DS682F3
8.2.7 Peak Current (I1
PEAK
, I2
PEAK
) and Peak Voltage (V1
PEAK
, V2
PEAK
)
Address: 18 (I1
PEAK
), 19 (V1
PEAK
), 22 (I2
PEAK
), 23 (V2
PEAK
)
Peak current,
I1
PEAK
(I2
PEAK
) and peak voltage, V1
PEAK
(V2
PEAK
) are the instantaneous current and voltage
samples with the greatest magnitude detected during the last low-rate interval. These are two's complement
values in the range of -1.0
value 1.0, with the binary point to the right of the MSB.
8.2.8 Apparent Power (S1, S2)
Address: 20 (S1), 24 (S2)
Apparent power
S1 (S2) is the product of V1
RMS
and I1
RMS
(V2
RMS
and I2
RMS
), These are two's complement
values in the range of 0
value 1.0, with the binary point to the right of the MSB.
8.2.9 Power Factor (PF1, PF2)
Address: 21 (PF1), 25 (PF2)
Power factor is calculated by dividing active power by apparent power. The sign is determined by the active
power sign. These are two's complement values in the range of -1.0
value 1.0, with the binary point to the
right of the MSB.
8.2.10 Temperature (T) – Address: 27
T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a
two's complement value in the range of -128.0
value 128.0 (
o
C), with the binary point to the right of bit 16.
T can be rescaled by the application using the T
GAIN
and T
OFF
registers.
8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (E
PULSE,
S
PULSE,
Q
PULSE
)
Address: 29 (E
PULSE
), 30 (S
PULSE
), 31 (Q
PULSE
)
These drive the pulse outputs when configured to do so. If the Ichan bit in Modes is “0”, these registers are
driven from
P1
AVG
, S1, and Q1
AVG
, respectively. If the Ichan bit is “1”, these registers are driven from P2
AVG
,
S2, and Q2
AVG
, respectively. These are two's complement values in the range of -1.0 value 1.0, with the
binary point to the right of the MSB.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
7
)2
6
2
5
2
4
2
3
2
2
2
1
2
0
.....
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

CS5464-IS

Mfr. #:
Buy CS5464-IS
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators 3-Ch Single Phase Power/Energy IC
Lifecycle:
New from this manufacturer.
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