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CS5464-IS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
CS5464
DS682F3 31
8.2.12 Internal Status (Status) and Interrupt Mask (Mask)
Address: 15 (Status); 26 (Mask)
Default = 1 (
Status), 0 (Mask)
The
Status register indicates a variety of conditions within the chip. Writing a '1' to a Status register bit will clear
that bit if the condition that set it has been removed. Writing a '0' to any bit has no effect.
The
Mask register is used to control the activation of the INT pin. Placing a logic '1' to a Mask register bit will
allow the corresponding
Status register bit to activate the INT pin when set.
DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated.
It indicates completion of other commands and the reset sequence.
I1OR (I2OR) Current Out of Range. Set when the measured current would cause the
I1 (I2) register to
overflow.
V1OR (V2OR) Voltage Out of Range. Set when the measured voltage would cause the
V1 (V2) register to
overflow.
CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updat-
ed.
I1ROR (I2ROR) RMS Current Out of Range. Set when RMS current would cause the
I1
RMS
(I2
RMS
) register
to overflow.
V1ROR (V2ROR) RMS Voltage Out of Range. Set when RMS voltage would cause the
V1
RMS
(V2
RMS
) reg-
ister to overflow.
E1OR (E2OR) Energy Out of Range. Set when average power would cause
P1
AVG
(P2
AVG
) to overflow.
I1FAULT (I2FAULT)Indicates when a current fault condition has occurred.
V1SAG (V2SAG) Indicates when a voltage sag condition has occurred.
TUP Indicates when the Temperature register (
T) has been updated.
TOD Modulator oscillation has been detected in the temperature A/D.
VOD Modulator oscillation has been detected in the voltage A/D.
I1OD (I2OD) Modulator oscillation has been detected in the current1 (current2) A/D.
LSD Low Supply Detect. Set when the voltage on the PFMON pin falls below the specified low
level. LSD bit cannot be reset until the voltage rises above the specified high level.
FUP Frequency Updated. Indicates the
Epsilon register has been updated.
IC
Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may
also indicate loss of serial command synchronization and the part may need to be re-initial-
ized.
23 22 21 20 19 18 17 16
DRDY I2OR V2OR CRDY I2ROR V2ROR I1OR V1OR
15 14 13 12 11 10 9 8
E2OR I1ROR V1ROR E1OR I1FAULT V1SAG I2FAULT V2SAG
76543210
TUP TOD I2OD VOD I1OD LSD FUP
IC
CS5464
32 DS682F3
8.2.13 Control (Ctrl) – Address: 28
Default = 0
PC[7:0] Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is signed
and in the range of -1.0
value 1.0 sample (OWR) intervals.
I1gain (I2gain) Sets the gain of the current1 (current2) input.
0 = Gain is set for ±250mV range.
1 = Gain is set for ±50mV range.
STOP Terminates E
2
PROM command sequence (if used).
0 = No Action
1 = Stop E
2
PROM Commands.
INTOD Converts INT
output pin to an open drain output.
0 = Normal Output
1 = Open-drain Output
NOCPU Saves power by disabling the CPUCLK output pin.
0 = CPUCLK Enabled
1 = CPUCLK Disabled
NOOSC Disables the crystal oscillator, making XIN a logic-level input.
0 = Crystal Oscillator Enabled
1 = Crystal Oscillator Disabled
23 22 21 20 19 18 17 16
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
15 14 13 12 11 10 9 8
---I2gain---STOP
76543210
- - I1gain INTOD - NOCPU NOOSC -
CS5464
DS682F3 33
8.3 Page 1 Registers
8.3.1 DC Offset for Current (I1
OFF
, I2
OFF
) and Voltage (V1
OFF
, V2
OFF
)
Address: 0 (I1
OFF
), 2 (V1
OFF
), 7 (I2
OFF
), 9 (V2
OFF
)
Default = 0
DC offset registers
I1
OFF
& V1
OFF
(I2
OFF
& V2
OFF
) are initialized to zero on reset. During DC offset calibration,
selected registers are written with the inverse of the DC offset measured. The application program can also write
the DC offset register values. These are two's complement values in the range of -1.0
value 1.0, with the
binary point to the right of the MSB.
8.3.2 Gain for Current (I1
GAIN
, I2
GAIN
) and Voltage (V1
GAIN
, V2
GAIN
)
Address: 1 (I1
GAIN
), 3 (V1
GAIN
), 8 (I2
GAIN
), 10 (V2
GAIN
)
Default = 1.0
Gain registers
I1
GAIN
& V1
GAIN
(I2
GAIN
& V2
GAIN
)
are initialized to 1.0 on reset. During AC or DC gain calibration,
selected register are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point
values in the range of 0
value 4.0, with the binary point to the right of the second MSB.
8.3.3 Power Offset (P1
OFF
, P2
OFF
)
Address: 4 (P1
OFF
), 11 (P2
OFF
)
Default = 0
Power offset
P1
OFF
(P2
OFF
) is added to instantaneous power and averaged over a low-rate interval to yield
P1
AVG
(P2
AVG
) register results. It can be used to reduce systematic energy errors. These are two's complement
values in the range of -1.0
value 1.0, with the binary point to the right of the MSB.
8.3.4 AC Offset for Current (I1
ACOFF
, I2
ACOFF
) and Voltage (V1
ACOFF
, V2
ACOFF
)
Address: 5 (I1
ACOFF
), 6 (V1
ACOFF
), 12 (I2
ACOFF
), 13 (V2
ACOFF
)
Default = 0
AC offset registers
I1
ACOFF
& V1
ACOFF
(V
ACOFF
& V2
ACOFF
)
are initialized to zero on reset. These are added to
the RMS results before being stored to the RMS result registers. They can be used to reduce systematic errors
in the RMS results. These are two's complement values in the range of -1.0
value 1.0, with the binary point
to the right of the MSB.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
.....
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

CS5464-IS

Mfr. #:
Buy CS5464-IS
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators 3-Ch Single Phase Power/Energy IC
Lifecycle:
New from this manufacturer.
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