45
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
T
A
P
TAP
Cont-
roller
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
clkDR, ShiftDR
UpdateDR
TDO
TDI
TMS
TCLK
TRST
clklR, ShiftlR
UpdatelR
Instruction Register
Instruction Decode
Control Signals
5941 drw29
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V51233/72V51243/
72V51253 incorporates the necessary tap controller and modified pad cells to
implement the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
••
••
• Test Access Port (TAP)
••
••
• TAP controller
••
••
• Instruction Register (IR)
••
••
• Data Register Port (DR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 27. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
