MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
10
Maxim Integrated
store the display images. A memory plane is the exact
amount of memory required to store the display image.
The memory plane architecture allows one plane to be
used to refresh the display, while at least one other plane
is available to build up the next image. The global plane
counter register (Table 30) allows the plane used to
refresh the display to be selected either directly on com-
mand, or automatically under MAX6960 control.
Automatic plane switching can be set from 63 plane
changes a second to one plane change every 63s.
Display Memory Addressing
The MAX6960 contains 64 bytes of display mapping
memory. This display memory provides four memory
planes (of 16 bytes) when 1-bit-per-pixel intensity con-
trol is selected, or two memory planes (of 32 bytes)
when 2-bits-per-pixel intensity control is used (Table 6).
The 64 bytes of display memory in a MAX6960 could
be accessed with 6 bits of addressing on a driver-by-
driver basis.
The MAX6960 uses a 14-bit addressing scheme. The
address map encompasses up to 256 MAX6960 dri-
vers, all connected to the host through a common 4-
wire interface, and also interconnected through a local
3-wire interface. The purpose of the 3-wire interface is
to actively segment the 14-bit address space among
the (up to) 256 MAX6960s.
The total display memory is already partitioned among
these MAX6960 drivers in a register format. The
MAX6960s repartition these registers to appear as con-
tiguous planes of display memory, organized by color
(red, then green) and then into planes (P0 to P4)
(Table 6).
Register Addressing Modes
The MAX6960 accepts 8-bit, 16-bit, and 24-bit trans-
missions. All MAX6960s sharing an interface receive
and decode all these transmissions, but the content of
a transmission determines which MAX6960s store and
use a particular transmission, and which discard it
(Table 7).
PATTERN OF MULTIPLEX CYCLES FOR WHICH A PIXEL IS ENABLED
PIXEL
GRADUATION
BIT BIT
PIXEL
INTENSITY
SETTING
01234567891011
Both 1 1 Full 1 1 1 1 1 1 1 1 1 1 1 1
Arithmetic 1 0 2/3 1 0 1 1 0 1 1 0 1 1 0 1
Geometric 1 0 1/2 1 0 1 0 1 0 1 0 1 0 1 0
Arithmetic 0 1 1/3 0 1 0 0 1 0 0 1 0 0 1 0
Geometric 0 1 1/4 0 1 0 0 0 1 0 0 0 1 0 0
Both 0 0 Off 0 0 0 0 0 0 0 0 0 0 0 0
Table 5. Frame Modulation with Pixel Intensity
GLOBAL PANEL CONFIGURATION
REGISTER
PLANES/INTENSITY
(PI BIT)
COLOR
(C BIT)
PIXEL-LEVEL
INTENSITY
CONTROL
DISPLAY TYPE
DISPLAY MAPPING
ADDRESSES PER PLANE
DISPLAY
PLANES
AVAILABLE
0 0 1 bit per pixel Monocolor 16 red contiguous 4
0 1 1 bit per pixel RGY
8 red contiguous,
8 green contiguous
4
1 0 2 bits per pixel Monocolor
16 red contiguous,
16 red contiguous
2
1 1 2 bits per pixel RGY
16 red
(2 noncontiguous groups of 8),
16 green
(2 noncontiguous groups of 8)
2
Table 6. Panel Configuration
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
11
Maxim Integrated
8-Bit Transmissions
Eight-bit transmissions are write-only, data-only
accesses that write data to the display memory indi-
rected by the global display indirect address register
(Figure 6). The global display indirect address register
autoincrements after the write access. Eight-bit trans-
missions provide the quickest method of updating a
plane of display memory of the MAX6960. It is the most
suitable display update method if the host system
builds an image in local memory, and then dumps the
image into a display plane of the MAX6960.
16-Bit Transmissions
Sixteen-bit transmissions are read/write, command-
and-data accesses to the MAX6960’s configuration
registers (Figure 7). A write can generally be global
(updates all MAX6960s on the 4-wire bus with the same
data) or specific (updates just the MAX6960 indirected
by the global driver indirect address register). Note:
The global driver indirect address register selects a
specific MAX6960. This is not the same as the glob-
al display indirect address register, which points to
display memory that could be in any MAX6960. A
16-bit read is always indirected through the global dri-
ver indirect address register to select only one
MAX6960 to respond. When a read or write is indirect-
ed through the global driver indirect address register,
the 16-bit command can choose whether the global dri-
ver indirect address is autoincremented after the com-
mand has been executed. This allows the host to set up
one or more registers in consecutive MAX6960s with
the display indirect address, autoincrementing only
when required.
8-, 16-, OR 24-BIT DATA PACKET SENT TO MAX6960
DATA FORMAT
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
8-bit indirect display
memory addressing.
Address is global display
indirect address (14 bits)
stored as {MSB, LSB} in
{register 0x0A, register
0x09}.
8 bits of display memory
16-bit device addressing. R/W AI L/G 0
4-bit
address
8 bits of driver register data
Factory reserved; do not
write to this address.
—1
24-bit direct display
memory addressing
(monocolor 1 bit per
pixel).
R/W X
Planes
0, 1, 2, 3
12-bit addressing across 256 drivers,
4096 x 8 red pixels
8 bits of display memory
(1 bit per pixel)
24-bit direct display
memory addressing
(RGY 1 bit per pixel).
R/W X
Planes
0, 1, 2, 3
12-bit addressing across 256 drivers,
2048 x 8 red pixels, and
2048 x 8 green pixels
8 bits of display memory
(1 bit per pixel)
24-bit direct display
memory addressing
(monocolor 2 bits per
pixel).
R/W X
Planes
0, 1
13-bit addressing across 256 drivers,
4096 x 4 red pixels
8 bits of display memory
(2 bits per pixel)
24-bit direct display
memory addressing
(RGY 2 bits per pixel).
R/W X
Planes
0, 1
13-bit addressing across 256 drivers,
4096 x 4 red pixels, and
4096 x 4 green pixels
8 bits of display memory
(2 bits per pixel)
Table 7. Register Addressing Modes
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
12
Maxim Integrated
24-Bit Transmissions
Twenty-four-bit transmissions are read/write, address-
and-data accesses to the MAX6960’s display memory
(Figure 8). This is direct access to display memory
because the memory address is included in the 24-bit
transmission, compared with an 8-bit transmission,
which uses the memory address stored in the global
display indirect address register. Twenty-four-bit trans-
missions provide the random-access method of updat-
ing a plane of display memory of the MAX6960. It is the
most suitable display update method if the host system
builds an image directly in a display memory plane,
rather than in host local memory.
Host 4-Wire Serial Interface
Serial Addressing
The MAX6960 communicates to the host through a 4-
wire serial interface. The interface has three inputs:
clock (CLK), chip select (CS), and data in (DIN), and
one output, data out (DOUT). CS must be low to clock
data into the device, and DIN must be stable when
sampled on the rising edge of CLK. DOUT is used for
read access, and is stable on the rising edge of CLK.
DOUT is high impedance except during MAX6960 read
accesses. Multiple MAX6960s may be connected to the
same 4-wire interface, with all devices connected to all
four interface lines in parallel. The normal limit of paral-
leled MAX6960s is 256, because that is the intercon-
nection limit for the 3-wire interface and associated
device addressing. The
Applications Information
sec-
tion discusses some practical issues raised by driving
many devices in parallel from the same interface.
The serial interface responds to only 8-bit, 16-bit, and
24-bit commands (Table 7).
The MAX6960 ignores any transmission that is not
exactly 8 bits, 16 bits, or 24 bits between the falling
and subsequent rising edge of CS.
Control and Operation Using the 4-Wire Interface
Controlling the MAX6960 requires sending an 8-bit, 16-
bit, or 24-bit word. The last byte, D7 through D0, is
always the data byte. Eight-bit accesses are write-only
accesses; 16-bit or 24-bit accesses are read or write
accesses, as determined by the MSB of the transmis-
sion, which is set for a read access; clear for a write. A
16-bit or 24-bit read involves transmitting 16 or 24 bits
to DIN, taking CS high, and then reading back 8 bits
from DOUT. Only one MAX6960’s DOUT is enabled
from tri-state for readback. The selected MAX6960’s
DOUT normally returns to tri-state after the 8th falling
edge of CLK. However if CS falls during the read
before the 8th falling edge of CLK, then the readback is
terminated and the selected MAX6960’s DOUT returns
to tri-state.
If a number of bits other than exactly 8 bits, 16 bits, or
24 bits are clocked into the MAX6960 between taking
CS low and taking CS high again, then that transmis-
sion is ignored.
Writing Device Registers
The MAX6960 is written to using the following
sequence (Figures 3, 4, and 5):
1) Take CLK low.
2) Take CS low.
3) For an 8-bit transmission:
Clock 8 bits of data into DIN, D7 first to D0 last,
observing the setup and hold times.
For a 16-bit transmission:
Clock 16 bits of data into DIN, D15 first to D0 last,
Dn Dn-1
t
CSS
t
DS
t
DH
t
CL
t
CH
D1 D0
t
CP
t
CSH
t
CSW
.
t
DO
CS
CLK
DIN
DOUT
D7 D6 D1 D0
t
DO
t
DO
Figure 5. Timing Diagram

MAX6961ATH+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LED Display Drivers 8x8 Matrix Graphic LED Driver
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