MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
24
Maxim Integrated
Planes/Intensity Control (Bit D7)
The planes/intensity (PI) control bit in the global panel
configuration register selects whether the display mem-
ory is configured as four planes with 1-bit-per pixel per
color-intensity control, or two planes with 2-bits-per
pixel per color-intensity control. This bit is fixed at zero
for the MAX6961 and MAX6963, and a write to this bit is
ignored for these parts.
Pixel Intensity Scale Register
The pixel intensity scale register (Table 24) sets the
graduation type used when 2-bits-per-pixel intensity
control is selected by setting the PI bit (Table 22). The
pixel level-intensity control can be set to be either
arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4, 1/2,
full). The setting is made on a digit-by-digit basis, so
each color on an RGY or RGB panel can use the most
appropriate graduation type.
Digit Intensity Control
The digit 0 and digit 1 intensity registers (Tables 25 and
26) set the fractions of the panel intensity PWM value
that are applied to the two display digits. The PWM for
each digit is calculated as n/256th of the panel intensity
value, where n is the value in the digit’s digit 0/1 intensi-
ty register. The digit 0/1 intensity registers enable con-
figuring relative adjustments in digit intensity, while the
display panel is still controlled as a whole by the panel
intensity. These adjustments are typically used to cali-
brate out luminosity differences between LEDs from dif-
ferent batches. They can also be used to color balance
RGY displays so that, for example, full panel intensity of
a red-green panel is a consistent orange hue.
Panel Intensity Control
Digital control of panel display brightness is provided
by an internal pulse-width modulator, which is con-
trolled by the panel intensity register (Table 27). The
modulator scales the average segment current in 253
steps from a maximum of 255/256 down to 2/256 of the
peak current. The maximum effective PWM duty cycle
for a digit is therefore 254/256, given by the maximum
255/256 digit intensity multiplied by the maximum
255/256 panel intensity. The minimum interdigit blank-
ing time is therefore 4/256 of a cycle, or 4/256 x 122µs
digit period = 1.91µs.
Peak-Segment Current Selection
The LED drive current can be selected between either
a 40mA peak per segment and a lower 20mA peak cur-
rent on a digit-by-digit basis using the R
ISET0
and
R
ISET1
pins. R
ISET0
should be open circuit to select
20mA, or connected to GND to select 40mA segment
current for digit 0. R
ISET1
selects segment current for
