MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
19
Maxim Integrated
Device Configuration
The MAX6960s driving a display panel must be config-
ured before the panel can be used to display images.
The configuration involves the global panel configura-
tion register (Table 15–Table 22), the global driver
devices register (Table 13), and the global driver rows
register (Table 14). The global driver devices register
should be written with the total number of MAX6960s
interconnected on the 3-wire interface, minus 1 (Table
13). For the four panel examples shown in Figures 1
and 2, 24 MAX6960s are used, so the global driver
devices register should be written with the value 23, or
0x17.
The global driver rows register should be written with
the number of MAX6960s per panel row, minus 1
(Table 14). For the panel examples shown in Figure 1
and Figure 2, there are six MAX6960s per row, so the
global driver rows register should be written with the
value 5.
The values stored in the global driver devices register
and the global driver rows register, together with the C
and Pl bits in the global panel configuration register
(Tables 21 and 22), are used by the 3-wire interface
configuration engine to reconfigure display memory
addressing among the interconnected MAX6960s.
Global Panel Configuration Register
The global panel configuration register contains eight
device settings (Table 15 to Table 22).
Shutdown Mode (Bit D0)
Shutdown mode is exited by clearing the S bit in the
global panel configuration register (Table 16). When
the MAX6960 is in shutdown mode, LED driver outputs
ROW1–ROW8 and COL1–COL16 are tri-stated, and
multiplexing is halted. Data in the global configuration
registers remains unaltered. For minimum supply cur-
rent in shutdown mode, logic inputs should be at GND
or V+ potential. Shutdown mode is exited by setting the
S bit in the global panel configuration register.
Invert Pixels (Bit D1)
The invert pixels (IP) bit in the global panel configura-
tion register controls whether the display memory is
used directly or inverted (Table 17).
together.
with a 0.9537µs delay between adjacent devices.
multiplex timing shown in Figure 11.
Figure 12.
