MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
25
Maxim Integrated
REGISTER DATA
REGISTER
ADDRESS CODE
(HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Global display indirect address LSB 0x09 D7 D6 D5 D4 D3 D2 D1 D0
Global display indirect address MSB 0x0A X X D13 D12 D11 D10 D9 D8
Table 29. Global Display Indirect Address Format
REGISTER DATA
REGISTER
PLANES/INTENSITY BIT
(SEE TABLE 22):
0 FOR 1 BIT/PIXEL;
4 PLANES
1 FOR 2 BIT/PIXEL;
2 PLANES
ADDRESS
CODE
(HEX)
D7 D6 D5 D4 D3 D2 D1 D0
PLANE COUNTER 0x0B
Fast
slow
Auto
manual
Counter setting
Manual selection to plane 0—counter
disabled
X 0x0B X 0 X X X X 0 0
Manual selection to plane 1—counter
disabled
X 0x0B X 0 X X X X 0 1
Manual selection to plane 2—counter
disabled
0 0x0B X 0 X X X X 1 0
Manual selection to plane 0—counter
disabled
1 0x0B X 0 X X X X 1 0
Manual selection to plane 3—counter
disabled
0 0x0B X 0 X X X X 1 1
Manual selection to plane 1—counter
disabled
1 0x0B X 0 X X X X 1 1
SLOW PLANE COUNTER 0 1 XXXXXX
Auto slow plane counter—1 frame
every second
0x0B 0 1 0 0 0 0 0 1
Auto slow plane counter—1 frame
every 2s
0x0B 0 1 0 0 0 0 1 0
0 1 ——————
Auto slow plane counter—1 frame
every 62s
0x0B 0 1 1 1 1 1 1 0
Auto slow plane counter—1 frame
every 63s
0x0B 0 1 1 1 1 1 1 1
FAST PLANE COUNTER 1 1 XXXXXX
Auto fast plane counter—1 frame per
second
0x0B 1 1 0 0 0 0 0 1
Table 30. Global Plane Counter Register Format
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
26
Maxim Integrated
digit 1 in the same manner. The MAX6960 is guaran-
teed to drive 40mA peak segment current into a 2.4V
LED with a minimum supply voltage of 3.15V, and
20mA peak segment current into a 2.2V LED with a
minimum supply voltage of 2.7V.
Global Driver Indirect Address Register
The global driver indirect address register is used to
store the driver address identifying which of 256
MAX6960s is accessed for 16-bit transmission when a
local register is read (Table 28).
Global Display Indirect Address Register
The global display indirect address registers are used
to store the 14-bit display memory address identifying
which byte of display memory across all the intercon-
nected MAX6960s is written by an 8-bit transmission
(Table 29). The 14-bit address stored in these two reg-
isters increments after every 8-bit transmission, and
overflows from address 0x3FFF to address 0x0000.
Global Plane Counter
The global plane counter (Table 30) allows any display
plane to be selected as the current display plane, or
configures the MAX6960 for automatic plane sequenc-
ing. The display plane is switched to the newly selected
plane on the rising edge of CS at the end of the 16-bit
transmission. When automatic plane sequencing is
selected, the current display plane is initialized to plane
P0. The current display plane is incremented through
all four planes P0–P3 (planes/intensity = 0) or both
planes P0–P1 (planes/intensity = 1) at the frame rate
selected, and then restarts at plane P0 again. The
plane sequencing continues until the global plane
counter is reconfigured. If the global plane counter is
used for the automatic sequencing of animations, the
user should ensure that the plane ahead of the current
display plane is updated before the automatic plane
switchover to achieve artifact-free animation.
Global Clear Planes Command
Writing the global clear planes counter (Table 31) allows
any or all display memory planes to be cleared with one
command. The selected plane(s) are cleared on the ris-
ing edge of CS at the end of the 16-bit transmission.
Fault Detection
LED Fault Detection
The MAX6960 detects open-circuit and short-circuit
LEDs. It can only detect an LED fault when attempting
to light that LED, so a good strategy to check a panel is
to program the panel with all LEDs on power-up to
check the displays.
The fault and device ID register (Table 32) uses 3 bits
to flag and distinguish open-circuit (open flag), short
circuit (short flag), and overtemperature (OT flag)
faults, and a fourth flag (fault flag), which is an OR of
the open flag, short flag, and OT flag.
The fault and device ID register is cleared on power-
up, and can also be cleared by writing to it. The fault
flags are NOT cleared by a read. When writing the fault
and device ID register, the data written is ignored; all
fault flags are cleared, including the OT flag. It is possi-
ble to clear all MAX6960s on a bus by performing a
global write to the fault and device ID register.
REGISTER DATA
REGISTER
PLANES/INTENSITY BIT
(SEE TABLE 22):
0 FOR 1 BIT/PIXEL;
4 PLANES
1 FOR 2 BIT/PIXEL;
2 PLANES
ADDRESS
CODE
(HEX)
D7 D6 D5 D4 D3 D2 D1 D0
PLANE COUNTER 0x0B
Fast
slow
Auto
manual
Counter setting
Auto fast plane counter—2 frames per
second
0x0B 1 1 0 0 0 0 1 0
1 1 —————
Auto fast plane counter— 62 frames
per second
0x0B 1 1 1 1 1 1 1 0
Auto fast plane counter— 63 frames
per second
0x0B 1 1 1 1 1 1 1 1
Table 30. Global Plane Counter Register Format (continued)
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
27
Maxim Integrated
REGISTER DATA
REGISTER
ADDRESS
CODE
(HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Fault (read) 0x05
Fault
flag
Part ID X X OT flag
Short
flag
Open
flag
Fault (write) clears fault register status 0x05 0 Part ID X X 0 0 0
Device is MAX6960 0x05 X 0 0 X X X X X
Device is MAX6961 0x05 X 0 1 X X X X X
Device is MAX6962 0x05 X 1 0 X X X X X
Device is MAX6963 0x05 X 1 1 X X X X X
No LED or OT faults 0x05 0 Part ID X X 0 0 0
At least one open-circuit LED fault 0x05 1 Part ID X X X X 1
At least one short-circuit LED fault 0x05 1 Part ID X X X 1 X
Overtemperature fault 0x05 1 Part ID X X 1 X X
Table 32. Fault and Device ID Register Format
REGISTER DATA
ACTION
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
GLOBAL CLEAR PLANES 0x0C
GREEN
P3
GREEN
P2
GREEN
P1
GREEN
P0
RED P3 RED P2 RED P1 RED P0
Clear all red plane P0
display memory
0x0C X XXXXXX1
Clear all red plane P1
display memory
0x0C X XXXXX1X
Clear all red plane P2
display memory*
0x0C X XXXX1XX
Clear all red plane P3
display memory*
0x0C X X X X 1 X X X
Clear all green plane P0
display memory
0x0C X X X 1 X X X X
Clear all green plane P1
display memory
0x0C X X 1 XXXXX
Clear all green plane P2
display memory
†*
0x0C X 1 XXXXXX
Clear all green plane P3
display memory
†*
0x0C 1 XXXXXXX
Table 31. Global Clear Planes Register Format
*
These bit settings are ignored when the global panel configuration register bit PI is clear (i.e., ignored in 2-bits-per-pixel mode).
These bit settings are ignored when the global panel configuration register bit C is clear (i.e., ignored in monocolor mode).

MAX6961ATH+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LED Display Drivers 8x8 Matrix Graphic LED Driver
Lifecycle:
New from this manufacturer.
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