OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC1852CFW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC1852/LTC1853
13
18523fa
LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail
Voltage Feedback Amplifi er. Single 3V to ±15V supplies.
20mA supply current. Lowest distortion.
LT1812/LT1813: Single and Dual 100MHz Voltage Feed-
back Amplifi er. Single 5V to ±5V supplies. 3.6mA supply
current. Low noise and low distortion.
Input Filtering
The noise and the distortion
of the input amplifi er and
other circuitry must
be considered since they will add to
the LTC1852/LTC1853 noise and distortion.
Noisy input
circuitry should be fi ltered prior to the analog inputs to
minimize noise.
A simple 1-pole RC fi lter is
suffi cient for
many applications.
For instance, a 200Ω source resistor
and a 1000pF capacitor to ground on the input will limit
the input bandwidth to 800kHz.The capacitor also acts
as a charge reservoir for the input sample-and-hold and
isolates the ADC input from sampling glitch sensitive
circuitry.
High quality capacitors and resistors should be
used since these components can add distortion.
NPO
and silver mica type dielectric capacitors have excellent
linearity.
Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering.
Metal fi lm surface mount resistors
are much less susceptible to both problems.
REFERENCE
The LTC1852/LTC1853 includes an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.500V and has a very fl exible
3-pin interface. REFOUT is the 2.5V bandgap output, REFIN
is the input to the reference buffer and REFCOMP is the
reference buffer output. The input span is determined by
the voltage appearing on the REFCOMP pin as shown in
Table 2. The reference buffer has a gain of 1.6384 and
is factory trimmed by forcing an external 2.500V on the
REFIN pin and trimming REFCOMP to 4.096V. The 3-pin
interface allows for three pin-strappable Reference modes
as well as two additional external Reference modes. For
voltages on the REFIN pin ranging from 1V to 2.6V, the
output voltage on REFCOMP will equal 1.6384 times the
voltage on the REFIN pin. In this mode, the REFIN pin can
be tied to REFOUT to use the internal 2.5V reference to get
4.096V on REFCOMP or driven with an external reference
or DAC. If REFIN is tied low, the internal 2.5V reference
divided by 2 (1.25V) is connected internally to the input
of the reference buffer resulting in 2.048V on REFCOMP.
If REFIN is tied high, the reference buffer is disabled and
REFCOMP can be tied to REFOUT to achieve a 2.5V span
or driven with an external reference or DAC. Table 3 sum-
marizes the Reference modes.
Table 3. Reference Mode Table
MODE REFIN REFCOMP
REFIN Tied Low 0V Input 2.048V Output
REFIN is Buffer Input 1v to 2.6 Input 1.6384V to 4.26V Output
(1.6384 • REFIN)
REFIN Tied High 5V Input Input, 19.2kΩ to Ground
Full Scale and Offset
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero dur-
ing a calibration sequence. Offset error must be adjusted
before full-scale error. Zero offset is achieved by adjust-
ing the offset applied to the “–” input. For single-ended
inputs, this offset should be applied to the COM pin. For
differential inputs, the “–” input is dictated by the MUX
address. For zero offset error, apply 0.5LSB (actual volt-
age will vary with input span selected) to the “+” input
and adjust the offset at the “–” input until the output code
fl ickers between 0000 0000 0000 and 0000 0000 0001
for the LTC1853 and between 00 0000 0000 and 00 0000
0001 for the LTC1852.
As mentioned earlier, the internal reference is factory
trimmed to 2.500V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed to 4.096V with an extremely accurate
external 2.5V reference applied to REFIN. Likewise, to make
sure that the full-scale gain trim is not compensating for
errors in the reference buffer gain, the input full-scale gain
is trimmed with an extremely accurate 4.096V reference
applied to REFCOMP (REFIN = 5V to disable the reference
buffer). This allows the use of either a 2.5V reference applied
to REFIN or a 4.096V reference applied to REFCOMP to
achieve accurate results. Full-scale errors can be trimmed
to zero by adjusting the appropriate reference voltage. For
unipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
APPLICATIONS INFORMATION
LTC1852/LTC1853
14
18523fa
INPUT VOLTAGE (V)
–FS –1LBS 0 1LBS FS – 1LBS
OUTPUT CODE
0111...1111
0111...1110
0111...1101
0000...0001
0000...0000
1111...1111
1111...1110
1000...0010
1000...0001
1000...0000
18523 F01B
BIPOLAR
ZERO
FS =
V
REFCOMP
2
SINGLE-ENDED/
DIFFERENTIAL BIT
UNIPOLAR/
BIPOLAR BIT
S6 S5
A2 A0
END OF
SEQUENCE BIT
PGA BIT
18523 F01
A1
MUX ADDRESS
S4 S3 S2 S1 S0
adjusted until the output code fl ickers between 1111 1111
1110 and 1111 1111 1111 for the LTC1853 and between
11 1111 1110 and 11 1111 1111 for the LTC1852.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code fl ickers between 0111 1111
1110 and 0111 1111 1111 for the LTC1853 and between
01 1111 1110 and 01 1111 1111 for the LTC1852.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifi ca-
tions in the Converter Characteristics table.
OUTPUT DATA FORMAT
The LTC1852/LTC1853 have a 14 bit/16-bit parallel out-
put. The output word normally consists of a 10-bit/12-bit
conversion result data word and a 4-bit address (three
address bits A2
OUT
, A1
OUT
, A0
OUT
and the DIFF
OUT
bit).
The output drivers are enabled when RD is low provided
the chip is selected (CS is low). All 14/16 data output pins
and BUSY are supplied by OV
DD
and OGND to allow easy
interface to 3V or 5V digital logic.
The data format of the conversion result is automatically
selected and determined by the UNI/BIP input pin. If
the UNI/BIP pin is low indicating a unipolar input span
(0 – REFCOMP assuming PGA = 1), the format for the
data is straight binary with 1 LSB = FS/4096 (1mV for
REFCOMP = 4.096V). For the LTC1853 and 1LSB = FS/1024
(4mV for REFCOMP = 4.096V) for the LTC1852.
If the UNI/BIP pin is high indicating a bipolar input span
(± REFCOMP/2 for PGA = 1), the format for the data is two’s
complement binary with 1 LSB = [(+FS) – (–FS)]/4096
(1mV for REFCOMP = 4.096V). For the LTC1853 and 1LSB
= [(+FS) – (–FS)]/1024 (4mV for REFCOMP = 4.096V) for
the LTC1852.
In both cases, the code transitions occur midway be-
tween successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, ... –1.5LSB, –0.5LSB, 0.5LSB, 1.5LSB, ...
FS – 1.5LSB, FS – 0.5LSB).
The three most signifi cant bits of the data word (D11, D10
and D9 for the LTC1853; D9, D8 and D7 for the LTC1852)
also function as output bits when reading the contents of
the programmable sequencer. During readback, a 7-bit
status word (S6-S0) containing the contents of the cur-
rent sequencer location is available when RD is low. The
individual bits of the status word are outlined in Figure 1.
During readback, the D8 to D0 pins (LTC1853) or D6 to
D0 pins (LTC1852) remain high impedance irrespective
of the state of RD.
Figure 1. Readback Status Word
Unipolar Transfer Characteristic
(UNI/BIP = 0)
Bipolar Transfer Characteristic
(UNI/BIP = 1)
APPLICATIONS INFORMATION
LTC1852/LTC1853
15
18523fa
BOARD LAYOUT AND BYPASSING
To obtain the best performance from the LTC1852/LTC1853,
a printed circuit board with ground plane is required. The
ground plane under the ADC area should be as free of
breaks and holes as possible, such that a low impedance
path between all ADC grounds and all ADC decoupling
capacitors is provided. It is critical to prevent digital noise
from being coupled to the analog inputs, reference or
analog power supply lines. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 34 (OGND), Pin 13 (GND), Pin 16 (GND) and all other
analog grounds should be connected to this single ana-
log ground point. The bypass capacitors should also be
connected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
In some applications, it may be desirable to connect the
OV
DD
to the logic system supply and OGND to the logic
system ground. In these cases, OV
DD
should be bypassed
to OGND instead of the analog ground plane.
Low impedance analog and digital power supply common
returns are essential to the low noise operation of the
ADC and the foil width for these tracks should be as wide
as possible. In applications where the ADC data outputs
and control signals are connected to a continuously ac-
tive microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the sucessive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversions or
by using three-state buffers to isolate the ADC bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1852/LTC1853 have differential inputs to mini-
mize noise coupling. Common mode noise on the “+”
and “–” inputs will be rejected by the input CMRR. The
LTC1852/LTC1853 will hold and convert the difference
between whichever input is selected as the “+” input and
whichever input is selected as the “–” input. Leads to the
inputs should be kept as short as possible.
SUPPLY BYPASSING
High quality, low series resistance ceramic 10μF bypass
capacitors should be used. Surface mount ceramic ca-
pacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10μF tantalum capacitors in parallel with 0.1μF ceramic
capacitors can be used. Bypass capacitors must be located
as close to the pins as possible. The traces connecting the
pins and the bypass capacitors must be kept short and
should be made as wide as possible.
DIGITAL INTERFACE
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs.
The internal
clock is factory trimmed to achieve a typical conversion
time of 1400ns, and a maximum conversion time over
the full operating temperature range of 2μs.
No external
adjustments are required. The guaranteed maximum
acquisition time is 150ns. In addition, a throughput
time of 2.5μs and a minimum sampling rate
of 400ksps
is guaranteed.
SHDN
CONVST
t
4
18523 F03
CS
SHDN
t
3
18523 F02
Figure 3. SHDN to CONVST Wake-Up Timing
Figure 2. CS to SHDN Setup Timing
APPLICATIONS INFORMATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC1852CFW#PBF

Mfr. #:
Buy LTC1852CFW#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-bit, 8-ch. Parallel 400ksps ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet