LTC1852/LTC1853
19
18523fa
Table 5
OPERATION MODE M1 M0 WR RD COMMENTS
Direct Address 0
0
0
0
0 OE
OE
Address and Confi guration are Driven from External Pins
Address and Confi guration are Latched on Rising Edge of WR or Falling Edge of CONVST
Scan 0
0
1
1
0 OE
OE
Address is Provided by Internal Scan Counter, Confi guration is Driven from External Pins
Confi guraton is Latched on Rising Edge of WR or Falling Edge of CONVST
Program 1 0 1 Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and
Advances to Next Location
Readback 1 0 1 Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD
Advances to Next Location
Sequence Run 1 1 X OE Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to
Next Location
The sequencer is accessed by taking the M1 mode pin
high. With M1 high, the sequencer memory is accessed
by taking the M0 mode pin low. This will cause BUSY to
go low, disabling conversions during the programming
and readback of the sequencer. The sequencer is reset
to location 0000 whenever M1 or M0 changes state. One
of these signals should be cycled prior to any read or
write operation to guarantee that the sequencer will be
programmed or read starting at location 0000.
The sequencer is programmed sequentially starting from
location 0000. RD and WR should be held high, the ap-
propriate signals applied to the DIFF pin, the A2 to A0 MUX
address pins, the UNI/BIP pin and the PGA pin and WR
taken low to write to the memory. WR going high will latch
the data into memory and advance the pointer to the next
sequencer location. Up to 16 locations can be programmed
and the last location written before M0 is taken back high
will be the last location in the sequence. After 16 writes,
the pointer is reset to location 0000 and any subsequent
writes will erase all of the previous contents and start a
new sequence.
The sequencer memory can be read by holding WR high
and strobing RD. Taking RD low accesses the sequencer
memory and enables the data output pins. The sequencer
should be reset to location 0000 before beginning a read
operation (by applying a positive pulse to MO). The seven
output bits will be available on the DIFF
OUT
/S6, A2
OUT
/S5,
A1
OUT
/S4, A0
OUT
/S3, D11/S2, D10/S1 and D9/S0 pins
(LTC1853) or DIFF
OUT
/S6, A2
OUT
/S5, A1
OUT
/S4, A0
OUT
/S3,
D9/S2, D8/S1 and D7/S0 pins (LTC1852). The D8 to D0
(LTC1853) or D6 to D0 (LTC1852) data output pins will
remain high impedance during readback. RD going high
will return the data output pins to a high impedance state
and advance the pointer to the next location. A logic 1
on the D9/S0 (D7/S0) pin indicates the last location in
the current sequence but all 16 locations can be read by
continuing to clock RD. After 16 reads, the pointer is reset
to location 0000. When all programming and/or reading
of the sequencer memory is complete, M0 is taken high.
BUSY will come back high enabling CONVST and indicating
that the part is ready to start a conversion.
Sequence Run Mode
Once the sequencer is programmed, M0 is taken high.
BUSY will also come back high enabling CONVST and
the next falling CONVST will begin a conversion using the
MUX address and input confi guration stored in location
0000 of the sequencer memory. After each conversion,
the sequencer pointer is advanced by one and the MUX
address ( the actual channel or channels being converted,
not the sequencer pointer) for the present conversion
is available on the address output pins along with the
conversion result. When the sequencer fi nishes convert-
ing the last programmed location, the sequencer pointer
will return to location 0000 for the next conversion. The
sequencer will also reset to location 0000 anytime the M1
or M0 pin changes state.
The contents of the sequencer memory will be retained
as long as power is contiuously applied to the part. This
allows the user to switch from Sequence Run mode to
either Direct Address or Scan Mode and back without
losing the programmed sequence. The part can also be
disabled using CS or shutdown in Nap or Sleep mode
without losing the programmed sequence. Table 5 outlines
the operational modes of the LTC1852/LTC1853. Figures 11
and 12 show the timing diagrams for writing to, reading
from and running a sequence.
APPLICATIONS INFORMATION
