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LTC1852CFW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC1852/LTC1853
7
18523fa
PIN FUNCTIONS
CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can
be used single ended relative to the analog input common
pin or differentially in pairs (CH0 and CH1, CH2 and CH3,
CH4 and CH5, CH6 and CH7).
COM (Pin 9): Analog Input Common Pin. For single-ended
operation (DIFF = 0), COM is the “–” analog input. COM
is disabled when DIFF is high.
REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass
to analog ground plane with 1μF.
REFIN (Pin 11): Reference Mode Select/Reference Buffer
Input. REFIN selects the reference mode and acts as the
reference buffer input. REFIN tied to ground (Logic 0) will
produce 2.048V on the REFCOMP pin. REFIN tied to the
positive supply (Logic 1) disables the reference buffer
to allow REFCOMP to be driven externally. For voltages
between 1V and 2.6V, the reference buffer produces an
output voltage on the REFCOMP pin equal to 1.6384 times
the voltage on REFIN (4.096V on REFCOMP for a 2.5V
input on REFIN).
REFCOMP (Pin 12): Reference Buffer Output. REFCOMP
sets the full-scale input span. The reference buffer produces
an output voltage on the REFCOMP pin equal to 1.6384
times the voltage on the REFIN pin (4.096V on REFCOMP
for a 2.5V input on REFIN). REFIN tied to ground will
produce 2.048V on the REFCOMP pin. REFCOMP can be
driven externally if REFIN is tied to the positive supply.
Bypass to analog ground plane with 10μF tantalum in
parallel with 0.1μF ceramic or 10μF ceramic.
GND (Pins 13, 16): Ground. Tie to analog ground plane.
V
DD
(Pins 14, 15): Positive Supply. Bypass to analog
ground plane with 10μF tantalum in parallel with 0.1μF
ceramic or 10μF ceramic.
DIFF
OUT
/S6 (Pin 17): Three-State Digital Data Output.
Active when RD is low. Following a conversion, the
single-ended/differential bit of the present conversion is
available on this pin concurrent with the conversion result.
In Readback mode, the single-ended/differential bit of the
current sequencer location (S6) is available on this pin.
The output swings between OV
DD
and OGND.
A2
OUT
/S5, A1
OUT
/S4, A0
OUT
/S3 (Pins 18 to 20): Three-
State Digital MUX Address Outputs. Active when RD is low.
Following a conversion, the MUX address of the present
conversion is available on these pins concurrent with the
conversion result. In Readback mode, the MUX address of
the current sequencer location (S5-S3) is available on these
pins. The outputs swing between OV
DD
and OGND.
D9/S2 (Pin 21, LTC1852): Three-State Digital Data Output.
Active when RD is low. Following a conversion, bit 9 of the
present conversion is available on this pin. In Readback
mode, the unipolar/bipolar bit of the current sequencer
location (S2) is available on this pin. The output swings
between OV
DD
and OGND.
D11/S2 (Pin 21, LTC1853): Three-State Digital Data Output.
Active when RD is low. Following a conversion, bit 11 of
the present conversion is available on this pin. In Readback
mode, the unipolar/bipolar bit of the current sequencer
location (S2) is available on this pin. The output swings
between OV
DD
and OGND.
D8/S1 (Pin 22, LTC1852): Three-State Digital Data Outputs.
Active when RD is low. Following a conversion, bit 8 of the
present conversion is available on this pin. In Readback
mode, the gain bit of the current sequencer location (S1)
is available on this pin. The output swings between OV
DD
and OGND.
D10/S1 (Pin 22, LTC1853): Three-State Digital Data
Outputs. Active when RD is low. Following a conversion,
bit 10 of the present conversion is available on this pin.
In Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OV
DD
and OGND.
D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs.
Active when RD is low. Following a conversion, bit 7 of the
present conversion is available on this pin. In Readback
mode, the end of sequence bit of the current sequencer
location (S0) is available on this pin. The output swings
between OV
DD
and OGND.
LTC1852/LTC1853
8
18523fa
D9/S0 (Pin 23, LTC1853): Three-State Digital Data Outputs.
Active when RD is low. Following a conversion, bit 9 of the
present conversion is available on this pin. In Readback
mode, the end of sequence bit of the current sequencer
location (S0) is available on this pin. The output swings
between OV
DD
and OGND.
D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OV
DD
and OGND.
D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OV
DD
and OGND.
NC (Pins 31 to 32, LTC1852): No Connect. There is no
internal connection to these pins.
BUSY (Pin 33): Converter Busy Output. The BUSY output
has two functions. At the start of a conversion, BUSY will
go low and remain low until the conversion is completed.
The rising edge may be used to latch the output data.
BUSY will also go low while the part is in Program/Read-
back mode (M1 high, M0 low) and remain low until M0
is brought back high. The output swings between OV
DD
and OGND.
OGND (Pin 34): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 35): Digital Data Output Supply. Normally tied
to 5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10μF tantalum in parallel with 0.1μF ceramic
or 10μF ceramic.
M0 (Pin 36): Mode Select Pin 0. Used in conjunction with
M1 to select operating mode. See Table 5.
PGA (Pin 37): Gain Select Input. A high logic level selects
gain = 1, a low logic level selects gain = 2.
UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low
selects a unipolar input span, a high logic level selects a
bipolar input span.
A0 to A2 (Pins 39 to 41): MUX Address Input Pins.
DIFF (Pin 42): Single-Ended/Differential Select Input.
A low logic level selects single ended, a high logic level
selects differential.
WR (Pin 43): Write Input. In Direct Address mode, WR
low enables the MUX address and confi guration input pins
(Pins 37 to 42). WR can be tied low or the rising edge of
WR can be used to latch the data. In Program mode, WR
is used to program the sequencer. WR low enables the
MUX address and confi guration input pins (Pins 37 to 42).
The rising edge of WR latches the data and increments
the counter to the next sequencer location.
RD (Pin 44): Read Input. During normal operation, RD
enables the output drivers when CS is low. In Readback
mode (M1 high, M0 low), RD going low reads the cur-
rent sequencer location, RD high advances to the next
sequencer location.
CONVST (Pin 45): Conversion Start Input. This active low
signal starts a conversion on its falling edge.
CS (Pin 46): Chip Select Input. The chip select input must
be low for the ADC to recognize the CONVST and RD inputs.
If SHDN is low, a low logic level on CS selects Nap mode;
a high logic level on CS selects Sleep mode.
SHDN (Pin 47): Power Shutdown Input. A low logic level
will invoke the Shutdown mode selected by the CS pin.
CS low selects Nap mode, CS high selects Sleep mode.
Tie high if unused.
M1 (Pin 48): Mode Select Pin 1. Used in conjunction with
M0 to select operating mode. See Table 5.
PIN FUNCTIONS
LTC1852/LTC1853
9
18523fa
PIN FUNCTIONS
PIN NAME DESCRIPTION MIN
NOMINAL (V)
TYP MAX
ABSOLUTE
MIN
MAXIMUM (M)
MAX
1 to 8 CH0 to CH7 Analog Inputs 0 V
DD
–0.3 V
DD
+ 0.3
9 COM Analog Input Common Pin 0 V
DD
–0.3 V
DD
+ 0.3
10 REFOUT 2.5V Reference Output 2.5 –0.3 V
DD
+ 0.3
11 REFIN Reference Buffer Input 0 2.5 V
DD
–0.3 V
DD
+ 0.3
12 REFCOMP Reference Buffer Output 4.096 –0.3 V
DD
+ 0.3
13 GND Ground 0 –0.3 V
DD
+ 0.3
14 V
DD
Positive Supply 2.7 5 5.5 –0.3 6
15 V
DD
Positive Supply 2.7 5 5.5 –0.3 6
16 GND Ground 0 –0.3 V
DD
+ 0.3
17 DIFF
OUT
/S6 Single-Ended/Differential Output OGND 0V
DD
–0.3 V
DD
+ 0.3
18 A2
OUT
/S5 MUX Address Output OGND 0V
DD
–0.3 V
DD
+ 0.3
19 A1
OUT
/S4 MUX Address Output OGND 0V
DD
–0.3 V
DD
+ 0.3
20 A0
OUT
/S3 MUX Address Output OGND 0V
DD
–0.3 V
DD
+ 0.3
21 D9/S2 (LTC1852) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
21 D11/S2 (LTC1853) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
22 D8/S1 (LTC1852) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
22 D10/S1 (LTC1853) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
23 D7/S0 (LTC1852) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
23 D9/S0 (LTC1853) Data Output OGND 0V
DD
–0.3 V
DD
+ 0.3
24 to 30 D6 to D0 (LTC1852) Data Outputs OGND 0V
DD
–0.3 V
DD
+ 0.3
24 to 32 D8 to D0 (LTC1853) Data Outputs OGND 0V
DD
–0.3 V
DD
+ 0.3
31 to 32 NC (LTC1852) No Connect
33 BUSY Converter Busy Output OGND 0V
DD
–0.3 V
DD
+ 0.3
34 OGND Output Ground 0 –0.3 V
DD
+ 0.3
35 OV
DD
Output Supply 2.7 5 5.5 –0.3 6
36 M0 Mode Select Pin 0 0 V
DD
–0.3 6
37 PGA Gain Select Input 0 V
DD
–0.3 6
38 UNI/BIP Unipolar/Bipolar Input 0 V
DD
–0.3 6
39 to 41 A0 to A2 MUX Address Inputs 0 V
DD
–0.3 6
42 DIFF Single-Ended/Differential Input 0 V
DD
–0.3 6
43 WR Write Input, Active Low 0 V
DD
–0.3 6
44 RD Read Input, Active Low 0 V
DD
–0.3 6
45 CONVST Conversion Start Input, Active Low 0 V
DD
–0.3 6
46 CS Chip Select Input, Active Low 0 V
DD
–0.3 6
47 SHDN Shutdown Input, Active Low 0 V
DD
–0.3 6
48 M1 Mode Select Pin 1 0 V
DD
–0.3 6
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC1852CFW#PBF

Mfr. #:
Buy LTC1852CFW#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-bit, 8-ch. Parallel 400ksps ADC
Lifecycle:
New from this manufacturer.
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