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Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 05 — 17 December 2004 23 of 53
[1] All ports are in input only (high impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
[3] The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset source that affects these SFRs is power-on reset.
SBUF Serial port data buffer register 99H xx xxxxxxxx
Bit address 9F 9E 9D 9C 9B 9A 99 98
SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000
SSTAT Serial port extended status
register
BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000
SP Stack pointer 81H 07 00000111
Bit address 8F 8E 8D 8C 8B 8A 89 88
TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 ----0000000000
TH0 Timer 0 high 8CH 00 00000000
TH1 Timer 1 high 8DH 00 00000000
TL0 Timer 0 low 8AH 00 00000000
TL1 Timer 1 low 8BH 00 00000000
TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 00000000
TRIM Internal oscillator trim register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[5] [6]
WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
[4] [6]
WDL Watchdog load C1H FF 11111111
WFEED1 Watchdog feed 1 C2H
WFEED2 Watchdog feed 2 C3H
Table 9: P89LPC903 Special function registers
…continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
