P89LPC903FD,112 Datasheet P89LPC901FN,129, P89LPC902FD,112, P89LPC902FN,129 | P37-P39

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 17 December 2004 37 of 53

9397 750 14465

8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.18.10 The 9

bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

8.19 Analog comparators

One analog comparator is provided on the P89LPC901. Two analog comparators are

provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such

that the output is a logical one (which may be read in a register) when the positive

input is greater than the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a zero. The comparator may be conﬁgured to cause

an interrupt when the output value changes.

The connections to the comparator are shown in Figure 19. Note: Not all possible

comparator conﬁgurations are available on all three devices. Please refer to the Logic

diagrams in Section 6 “Logic symbols” on page 12. The comparator functions to

= 2.4 V.

When the comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 microseconds. The comparator interrupt should not be

enabled during that time, and the comparator interrupt ﬂag must be cleared before

the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx.

This will cause an interrupt if the comparator interrupt is enabled. The user should

therefore disable the comparator interrupt prior to disabling the comparator.

Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the

comparator.

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 17 December 2004 38 of 53

9397 750 14465

8.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to

as V

REF

, is 1.23 V ±10%.

8.21 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag

is set whenever the comparator output changes state. The ﬂag may be polled by

software or may be used to generate an interrupt.

8.22 Comparator and power reduction modes

The comparators may remain enabled when Power-down or Idle mode is activated,

but the comparators are disabled automatically in Total Power-down mode.

If the comparator interrupt is enabled (except in Total Power-down mode), a change

of the comparator output state will generate an interrupt and wake up the processor. If

the comparator output to a pin is enabled, the pin should be conﬁgured in the

push-pull mode in order to obtain fast switching times while in Power-down mode.

The reason is that with the oscillator stopped, the temporary strong pull-up that

normally occurs during switching on a quasi-bidirectional port pin does not take

place.

The comparator consumes power in Power-down and Idle modes, as well as in the

normal operating mode. This fact should be taken into account when system power

consumption is an issue. To minimize power consumption, the user can disable the

comparator via PCONA.5 or put the device in Total Power-down mode.

Fig 19. Comparator input and output connections.

Comparator 1

CN1

(P0.4) CIN1A

(P0.5) CMPREF

REF

OE1

Change Detect

CO1

CMF1

Interrupt

002aaa453

CMP1 (P0.6)

Change Detect

CMF2

Comparator 2

OE2

CO2

CMP2 (P0.0)

CN2

(P0.2) CIN2A

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 17 December 2004 39 of 53

9397 750 14465

8.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can

be used for bus address recognition or keypad recognition. The user can conﬁgure

the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)

is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad

Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when

the condition is matched while the Keypad Interrupt function is active. An interrupt will

be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register

(KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x

series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then

any key connected to Port 0 which is enabled by the KBMASK register will cause the

hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt

may be used to wake up the CPU from Idle or Power-down modes. This feature is

particularly useful in handheld, battery powered systems that need to carefully

manage power consumption yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held

longer than six CCLKs.

8.24 Watchdog timer

The Watchdog timer causes a system reset when it underﬂows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer

can only be reset by a power-on reset. When the Watchdog feature is disabled, it can

be used as an interval timer and may generate an interrupt. Figure 20 shows the

Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,

the watchdog is disabled. The Watchdog timer has a time-out period that ranges from

afewµs to a few seconds. Please refer to the

P89LPC901/902/903 User’s Manual

for

more details.

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P89LPC903FD,112

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