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P89LPC903FD,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 31 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.12.2 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except
for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin,
there will be a current flowing from the pin to V
DD
, causing extra power consumption.
Therefore, applying 5 V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.3 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to V
DD
.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.12.4 Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.
8.12.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.6 Port 0 analog functions
The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.12.4 “Input-only configuration”.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On
any reset, the PT0AD bits default to ‘0’s to enable digital functions.
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 32 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.12.7 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.
• After power-up all I/O pins, except P1.5, may be configured by software.
• Pin P1.5 is input only.
Every output on the P89LPC901/902/903 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to Table 13 “DC electrical characteristics” for
detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC901/902/903 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.13.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however, it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the operating voltage range for V
DD
is 2.7 V to 3.6 V,
and the brownout condition occurs when V
DD
falls below the brownout trip voltage,
V
BO
(see Table 13 “DC electrical characteristics”), and is negated when V
DD
rises
above V
BO
. If brownout detection is disabled, the operating voltage range for V
DD
is
2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the
device can operate at 2.4 V, otherwise continuous brownout reset may prevent the
device from operating.
For correct activation of Brownout detect, the V
DD
rise and fall times must be
observed. Please see Table 13 “DC electrical characteristics” for specifications.
8.13.2 Power-on detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.14 Power reduction modes
The P89LPC901/902/903 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 33 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.14.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.14.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC901/902/903 exits Power-down mode via any reset, or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage V
RAM
. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after V
DD
has
been lowered to V
RAM
, therefore it is highly recommended to wake up the processor
via reset in this case. V
DD
must be raised to within the operating range before the
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.
8.14.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: During a power cycle, V
DD
must fall below V
POR
(see Table 13 “DC electrical
characteristics”) before power is reapplied, in order to ensure a power-on reset.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

P89LPC903FD,112

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Buy P89LPC903FD,112
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 8SO
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