Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 7 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5. Pinning information
5.1 Pinning
Fig 4. P89LPC901 pinning (SO8).
handbook, halfpage
002aaa438
P89LPC901FD
1
2
3
4
8
7
6
5
V
SS
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5
P1.2/T0
V
DD
XTAL1/P3.1
CLKOUT/XTAL2/P3.0
RST/P1.5
Fig 5. P89LPC901 pinning (DIP8).
handbook, halfpage
002aaa469
P89LPC901FN
1
2
3
4
V
DD
XTAL1/P3.1
CLKOUT/XTAL2/P3.0
RST/P1.5
V
SS
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5
P1.2/T0
8
7
6
5
Fig 6. P89LPC902 pinning (SO8).
handbook, halfpage
002aaa439
P89LPC902FD
1
2
3
4
8
7
6
5
V
SS
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6
V
DD
P0.2/CIN2A/KBI2
P0.0/CMP2/KBI0
RST/P1.5
Fig 7. P89LPC902 pinning (DIP8).
handbook, halfpage
002aaa470
P89LPC902FN
1
2
3
4
V
DD
P0.2/CIN2A/KBI2
P0.0/CMP2/KBI0
RST/P1.5
V
SS
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6
8
7
6
5
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 8 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.2 Pin description
Fig 8. P89LPC903 pinning (SO8).
handbook, halfpage
002aaa440
P89LPC903FD
1
2
3
4
8
7
6
5
V
SS
P0.4/CIN1A/KBI4
P0.5/CMPREF/KBI5
P1.0/TxD
V
DD
P0.2/CIN2A/KBI2
P1.1/RxD
RST/P1.5
Table 3: P89LPC901 pin description
Symbol Pin Type Description
P0.0 to P0.6 I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
7 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input.
I KBI4 — Keyboard input 4.
6 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 9 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P1.0 to P1.5 Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to Section 8.12.1 “Port configurations” and Table 13 “DC
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
5 I/O P1.2 — Port 1 bit 2.
O T0 — Timer/counter 0 external count input or overflow output.
4IP1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level.
When system power is removed V
DD
will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V
DD
falls below the minimum specified operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
P3.0 to P3.1 I/O Port 3: Port 3 is an I/O port with a user-configurable output types. During reset Port 3
latches are configured in the input only mode with the internal pull-up disabled. The
operation of port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
3 I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).
O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK to TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer.
2 I/O P3.1 — Port 3 bit 1.
I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the real time clock/system timer.
V
SS
8IGround: 0 V reference.
V
DD
1IPower Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
Table 3: P89LPC901 pin description
…continued
Symbol Pin Type Description

P89LPC903FD,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 8SO
Lifecycle:
New from this manufacturer.
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