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72V3611L20PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
1
3.3 VOLT CMOS SyncFIFO
TM
64 x 36
IDT72V3611
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4657/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2014
FEATURES:
••
••
• 64 x 36 storage capacity
••
••
•
Supports clock frequencies up to 67MHz
••
••
•
Fast access times of 10ns
••
••
•
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
••
••
•
Synchronous data buffering from Port A to Port B
••
••
•
Mailbox bypass register in each direction
••
••
• Programmable Almost-Full (AF) and Almost-Empty (AE) flags
••
••
• Microprocessor Interface Control Logic
••
••
• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
••
••
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
••
••
• Passive parity checking on each Port
••
••
• Parity Generation can be selected for each Port
••
••
•
Available in space-saving 120-pin Thin Quad Flatpack (PF)
••
••
•
Green parts available, see ordering information
DESCRIPTION:
The IDT72V3611 is designed to run off a 3.3V supply for exceptionally low
power consumption. This device is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports clock frequen-
cies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual-
port FIFO buffers data from Port A to Port B. The FIFO operates in IDT Standard
mode and has flags to indicate empty and full conditions, and two programmable
flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected
number of words is stored in memory. Communication between each port can
take place through two 36-bit mailbox registers. Each mailbox register has a
flag to signal when new mail has been stored. Parity is checked passively on
each port and may be ignored if not desired. Parity generation can be selected
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
PEFA
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
EF
AE
36
B
0
- B
35
FF
AF
FS
0
FS
1
4657 drw01
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM
ARRAY
64 x 36
2
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
NOTES:
1. Pin 1 identifier in corner.
2. NC = No internal connection
TQFP (PNG120, order code: PF)
TOP VIEW
PIN CONFIGURATION
4657 drw 02
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EF
AE
NC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
for data read from each port. Two or more devices may be used in parallel to
create wider data paths.
The IDT72V3611 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to the port clock that writes data into its array (CLKA). The Empty
Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized
to the port clock that reads data from its array.
The IDT72V3611 is characterized for operation from 0°C to 70°C. This
device is fabricated using high speed, submicron CMOS technology.
3
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
Symbol Name I/O Description
A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A.
AE Almost-Empty Flag O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
in the FIFO is less than or equal to the value in the offset register, X.
AF Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Offset register, X.
B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B.
CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-A and can be
asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-B and can be
asynchronous or coincident to CLKA. EF and AE are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA Port-A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port-B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF Empty Flag O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty,
and reads from its memory are disabled. Data can be read from the FIFO to its output register
when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory.
ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FF Full Flag O FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and
writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by
the second LOW-to-HIGH transition of CLKA after reset.
FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four
preset values into the Almost-Full and Almost-Empty Offset register (X).
MBA Port-A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
MBB Port-B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects the FIFO output register data for output.
MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the
device is reset.
MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the
device is reset.
ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
EVEN Select ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA Port-A Parity Error O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
Flag [Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The
parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced
HIGH regardless of the state of A0-A35 inputs.
PIN DESCRIPTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

72V3611L20PF

Mfr. #:
Buy 72V3611L20PF
Manufacturer:
IDT
Description:
FIFO 64 x 36 SyncFIFO, 3.3V
Lifecycle:
New from this manufacturer.
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