14
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 7. Timing for
AEAE
AEAE
AE
when the FIFO is Almost-Empty
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Figure 6.
FFFF
FFFF
FF
Flag Timing and First Available Write when the FIFO is Full
CSB
EFB
W/RB
MBB
ENB
B0 -B35
CLKB
FF
CLKA
CSA
4657 drw 09
WRA
12
A0 - A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH2
t
A
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
WFF
t
ENS3
t
ENS2
t
DS
t
ENH2
t
DH
To FIFO
Previous Word in FIFO Output Register
Next Word From FIFO
LOW
LOW
LOW
HIGH
LOW
HIGH
FIFO Full
t
WFF
t
ENH3
AE
CLKA
ENB
4657 drw 10
ENA
CLKB
2
1
tENS2
tENH2
tSKEW2
(1)
tPAE tPAE
tENS2 tENH2
X Word in FIFO
(X+1) Words in FIFO
