9
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Functions
H X X X X Input None
L H L X X Input None
LHH L ↑ Input None
LHHH ↑ Input Mail2 Write
L L L L X Output None
LLHL ↑ Output FIFO Read
L L L H X Output None
LLHH ↑ Output Mail1 Read (set MBF1 HIGH)
CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Functions
H X X X X Input None
L H L X X Input None
LHH L ↑ Input FIFO Write
LHHH ↑ Input Mail1 Write
L L L L X Output None
LLHL ↑ Output None
L L L H X Output None
LLHH ↑ Output Mail2 Read (set MBF2 HIGH)
Almost-Full and
Almost-Empty Flag FS1 FS0 RST
Offset Register (X)
16 H H ↑
12 H L ↑
8LH↑
4LL↑
SIGNAL DESCRIPTION
RESET ( RST )
The IDT72V3611 is reset by taking the Reset (RST) input LOW for at
least four port-A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH
transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of the FIFO and forces the
Full Flag (FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH
transitions of CLKA. The device must be reset after power up before data is
written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select
(FS0, FS1) inputs. The values that can be loaded into the register are shown
in Table 1. For the relevant Reset timing and preset value loading timing
diagram, see Figure 2. The relevant Write timing diagram for Port A can be found
in Figure 3.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-
A Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35
outputs are in the high-impedance state when either CSA or W/RA is HIGH.
The A0-A35 outputs are active when both CSA and W/RA are LOW. Data
is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and
FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A. The state of
the port-B data (B0-B35) outputs is controlled by the port-B Chip Select
(CSB) and the port-B Write/Read select (W/RB). The B0-B35 outputs are in
the high-impedance state when either CSB or W/RB is HIGH. The B0-B35
outputs are active when both CSB and W/RB are LOW. Data is read from the
FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB
is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and EF is HIGH (see Table
3).
The relevant Read timing diagram for Port B can be found in Figure 4.
The setup and hold-time constraints to the port clocks for the port Chip
Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling
write and read operations and are not related to HIGH-impedance control of
the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip
Select and Write/Read select can change states during the setup and hold-time
window of the cycle.
TABLE 1 – FLAG PROGRAMMING
TABLE 2 – PORT-A ENABLE FUNCTION TABLE
TABLE 3 – PORT-B ENABLE FUNCTION TABLE
