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72V3611L20PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
16
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 11. ODD/
EVENEVEN
EVENEVEN
EVEN
, W/RA, MBA, and PGA to
PEFAPEFA
PEFAPEFA
PEFA
Timing
NOTE:
1. CSA = L and ENA = H.
Figure 12. ODD/
EVENEVEN
EVENEVEN
EVEN
, W/RB, MBB, and PGB to
PEFBPEFB
PEFBPEFB
PEFB
Timing
4657 drw 13
CLKB
ENB
B0 - B35
MBB
CSB
W/RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/RA
W1
t
ENS1
t
ENH1
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
PMR
t
ENS2
t
ENH2
t
DIS
W1 (Remains valid in Mail2 Register after read)
t
ENS1
t
ENH1
t
ENS1
t
ENH1
t
ENS1
t
ENH1
4657 drw 14
ODD/
EVEN
PEFA
PGA
MBA
W/RA
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
4657 drw 15
ODD/
EVEN
PEFB
PGB
MBB
W/RB
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
Figure 10. Timing for Mail2 Register and
MBF2MBF2
MBF2MBF2
MBF2
Flag
NOTE:
1. Port-A parity generation off (PGA = L)
NOTE:
1. CSB = L and ENB = H.
17
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
Figure 14. Parity Generation Timing when reading from the Mail1 Register
Figure 13. Parity Generation Timing when reading from the Mail2 Register
NOTE:
1. ENA = H.
NOTE:
1. ENB = H.
4657 drw 16
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/RA
Mail2 Data
Generated Parity
Generated Parity Mail2 Data
CSA
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
4657 drw 17
ODD/
EVEN
B8, B17,
B26, B35
PGB
MBB
W/RB
Mail1
Data
Generated Parity
Generated Parity
Mail1 Data
CSB
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
18
IDT72V3611 3.3V, CMOS SyncFIFO
TM
64 x 36 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Includes probe and jig capacitance.
Figure 15. Load Circuit and Voltage Waveforms
4657 drw 18
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330Ω
3.3V
510Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
tW
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
¯
OH
OV
¯
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
tS
th
tPLZ
tPHZ
tPZL
tPZH
tPD
tPD
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

72V3611L20PF

Mfr. #:
Buy 72V3611L20PF
Manufacturer:
IDT
Description:
FIFO 64 x 36 SyncFIFO, 3.3V
Lifecycle:
New from this manufacturer.
Delivery:
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