72V3611L20PF Datasheet 72V3611L15PFG8, 72V3611L15PFG, 72V3611L20PF8 | P4-P6

IDT72V3611 3.3V, CMOS SyncFIFO

64 x 36 COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O Description

PEFB Port-B Parity Error O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as

Flag (Port B) B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the parity

bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity

trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by

having CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced

HIGH regardless of the state of the B0-B35 inputs

PGA Port-A Parity I Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity

Generation generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8,

A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit

of each byte.

PGB Port-B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated

Generation is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17,

B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of

each byte.

RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the

EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1

and FS0 inputs to select Almost-Full and Almost-Empty flag offset.

W/RA Port-A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port A for a

Select LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state

when W/RA is HIGH.

W/RB Port-B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port B for a

Select LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state

when W/RB is HIGH.

IDT72V3611 3.3V, CMOS SyncFIFO

64 x 36 COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR

TEMPERATURE RANGE (Unless otherwise noted)

(1)

Symbol Rating Commercial Unit

VCC Supply Voltage Range –0.5 to +4.6 V

(2)

Input Voltage Range –0.5 to VCC+0.5 V

(2)

Output Voltage Range –0.5 to VCC+0.5 V

IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA

IOK Output Clamp Current, (VO = < 0 or VO > VCC) ±50 mA

IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA

ICC Continuous Current Through VCC or GND ±500 mA

TSTG Storage Temperature Range –65 to 150 °C

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at

these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended

periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

NOTES:

1. All typical values are at VCC = 3.3V, TA = 25°C.

2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).

IDT72V3611

Commercial

tCLK = 15 ns

Symbol Parameter Test Conditions Min.

Typ.

(1)

Max. Unit

VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V

VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V

ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 μA

ILO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 μA

ICC

(2)

Standby Current VCC = 3.6V, VI = VCC - 0.2V or 0 — — 500 μA

CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF

COUT Output Capacitance VO = 0, f = 1 MHZ — 8 — pF

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING

FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)

RECOMMENDED OPERATING

CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 3.0 3.3 3.6 V

IH High-Level Input Voltage 2 — VCC+0.5 V

IL Low-Level Input Voltage — — 0.8 V

IOH High-Level Output Current — — –4 mA

OL Low-Level Output Current — — 8 mA

A Operating Free-Air 0 — 70 °C

Temperature

IDT72V3611 3.3V, CMOS SyncFIFO

64 x 36 COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT72V3611 with CLKA and CLKB operating at frequency

fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize

the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation

below.

CALCULATING POWER DISSIPATION

With I

CC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3611 may be calculated by:

T = VCC x ICC(f) + Σ(CL x (VOH - VOL)

x fO)

where:

N = number of outputs = 36

CL = output capacitance load

fO = switching frequency of an output

OH = output high-level voltage

OL = output low-level voltage

When no read or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is

calculated by:

PT = VCC x fS x 0.025 mA/MHz

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

0 10 20 30 40 50 60 70

100

125

150

VCC = 3.3V

fS ⎯ Clock Frequency ⎯ MHz

ICC(f) ⎯ Supply Current ⎯ mA

fdata = 1/2 fS

A = 25°C

L = 0 pF

CC = 3.0V

4657 drw 04

VCC = 3.6V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

72V3611L20PF

Mfr. #:

Buy 72V3611L20PF

Manufacturer:

IDT

Description:

FIFO 64 x 36 SyncFIFO, 3.3V

Lifecycle:

New from this manufacturer.

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72V3611L20PF

72V3611L20PF

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