OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

DS28DG02E-3C+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
13 of 34
Table 1. Alarm Frequency Control
DY/DT AM4 AM3 AM2 AM1 ALARM OCCURRENCE
X X X X 1 Every second
X X X 1 0 Every minute, when the seconds match
X X 1 0 0 Every hour, when minutes and seconds match
X 1 0 0 0 Every day, when hours, minutes, and seconds match
1 0 0 0 0 Every week, when day, hours, minutes, and seconds match
0 0 0 0 0 Every month, when date, hours, minutes, and seconds match
Multifunction Control/Setup Register
ADDR b7 b6 b5 b4 b3 b2 b1 b0
134h
0 BME BTRP WDOS WDE OSCE CAE
There is general read and write access to this address. Bit 7 always reads 0; it cannot be written to 1. This register
is reset to 00h when the battery voltage ramps up. See Figure 5 for the use of the CAE, WDE, WDOS, and BME
bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
BIT DESCRIPTION BIT(S) DEFINITION
CAE: Clock Alarm
Enable
b0
Enable/disable control of the RTC/Calendar alarm.
Legend: 0 disabled (power-on default); 1 enabled
OSCE: RTC Oscillator
Enable
b1
Run/halt control of the RTC’s 32KHz oscillator
Legend: 0 halted (power-on default); 1 running
WDE: Watchdog Enable b2
Enable/disable control of the watchdog and its alarm.
Legend: 0 disabled (power-on default); 1 enabled
The watchdog timer is reset by changing WDE from 0 to 1, V
CC
ramp up
(Power-on reset) or applying a positive pulse at the WDI pin.
WDOS: Watchdog
Output Selection
b3
Pin selection for watchdog alarm signaling.
Legend: 0 WDOZ pin (power-on default); 1 ALMZ pin
BTRP: Battery Monitor
Trip Point
b5:b4
Selection of the nominal Battery Monitor Trip Point voltage.
Legend: 00b 1.75V (power-on default); 01b 2.00V;
10b 2.25V; 11b 2.50V
BME: Battery Monitor
Enable
b6
Enable/disable control of the Battery Monitor and its alarm.
Legend: 0 disabled (power-on default); 1 enabled
The battery test takes place a) after BME changes to 1, b) after V
CC
ramps up, c) every hour on the hour. The
RTC must be running (OSCE
= 1) for the battery monitor to function.
Alarm and Status Register
ADDR b7 b6 b5 b4 b3 b2 b1 b0
135h
0 BATA WPZV POR BOR CLKA WDA RST
There is general read access to this address; writing clears all bits to 0. Bit 7 always reads 0. See Figure 5 for the
use of the CLKA, WDA, and BATA bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
14 of 34
BIT DESCRIPTION BIT(S) DEFINITION
RST: Reset Flag b0
RSTZ pin activity indicator; set whenever there is a pulse at RSTZ;
cleared by writing to the Alarm and Status register.
V
CC
ramp up: 1; V
BAT
attach: 0
WDA: Watchdog Alarm b1
Watchdog Alarm indicator; set whenever the watchdog is enabled AND
the watchdog timer expires; cleared by writing to the Alarm and Status
register.
V
CC
ramp up: 0; V
BAT
attach: 0
CLKA: Clock Alarm b2
RTC/Calendar Alarm indicator; set whenever the clock alarm is enabled
AND RTC and RTC Alarm register match; cleared by writing to the
Alarm and Status register.
V
CC
ramp up: 0; V
BAT
attach: 0
BOR: Battery-On Reset
Flag
b3
Battery attach indicator; set whenever the voltage at V
BAT
ramps up
above V
BATmin
; cleared by writing to the Alarm and Status register.
V
CC
ramp up: not affected; V
BAT
attach: 1
POR: Power-On Reset
Flag
b4
Power-On Reset indicator; set whenever the voltage at V
CC
ramps up
above V
CCmin
; cleared by writing to the Alarm and Status register.
V
CC
ramp up: 1; V
BAT
attach: 0
WPZV: Hardware Write
Protect Value
b5
WPZ pin state readout; reports the logic state at the WPZ pin;
V
CC
ramp up: WPZ pin state; V
BAT
attach: not affected.
BATA: Battery Alarm b6
Low Battery indicator; set whenever the battery alarm is enabled AND if,
during a battery test, V
BAT
is below the selected V
BAT
trip point; cleared
by writing to the Alarm and Status register.
V
CC
ramp up: battery test if BME = 1; V
BAT
attach: 0
Figure 5. ALMZ, WDOZ, and RSTZ Generation
BME, CAE, WDE, WDOS are defined in the Control/Setup register.
BATA, CLKA, WDA are alarm signals readable through the Alarm/Status register.
VCLA is the alarm output of the V
CC
monitor.
WDE
WD
A
WDOS
VCL
A
Debounce
BME
BAT
A
CAE
CLK
A
WDOZ
RSTZ
ALMZ
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
15 of 34
MONITORING FUNCTIONS
The DS28DG02 has two voltage monitors: one for the V
CC
supply voltage and another one for the battery that
supplies the RTC and associated registers if V
CC
is switched off. If V
CC
falls below the V
TRIP
threshold the V
CC
monitor activates the open-drain RSTZ output, as shown in Figure 6. There is a delay of t
DEL
between crossing the
trip point and RSTZ going LOW. As long as V
CC
is above V
POR
or the device has a functioning battery backup, the
logic level at RSTZ does not exceed V
OLmax
. Without battery support, the state of the RSTZ output is undefined for
V
CC
values below V
POR
. When V
CC
ramps up, RSTZ remains at LOW until the V
TRIP
threshold is reached. As V
TRIP
is
crossed, the voltage at RSTZ rises until it reaches V
TRMS
, the manual reset release threshold. This activates the
debounce circuit, which holds RSTZ low for t
RST
. After t
RST
is expired, the voltage at RSTZ ramps up to the value of
the applied pullup voltage.
Figure 6. RSTZ Power-Fail Reset
V
CC
V
TRIP
V
POR
V
CC
*
RSTZ
With the V
BAT
pin tied to V
CC
, the RSTZ behavior for
V
CC
< V
POR
is undefined.
*
V
CC
or the applicable pullup voltage for the RSTZ pin.
t
DEL
t
RST
A
s V
TRIP
is crossed, the voltage at
RSTZ starts rising, which triggers
the manual switch debounce
circuit and activates RSTZ for t
RST
.
The RSTZ pin is internally connected to a debounce circuit, which allows using a manually operated switch to
generate a reset signal. Figure 7 illustrates the timing of the manual reset. As the switch closes, it forces the
voltage at RSTZ to fall below V
ILmax
, which triggers the debounce circuit. Now the voltage at RSTZ is held at logic
LOW by both, the manual switch and the debounce circuit. When the manual switch is opened or t
DEB
is over,
(whichever occurs later) the voltage at RSTZ rises until it reaches V
TRMS
. This again triggers the debounce circuit,
which holds RSTZ low for t
RST
, after which the voltage at RSTZ ramps up to the pullup voltage. The minimum LOW
time of a manually generated reset is t
DEB
+ t
RST
.
Figure 7. RSTZ Manual Switch Debounce
RSTZ held low by
DS28DG02
Open
Manual
Switch
closed
V
CC
*
RSTZ
For t
RST
to start, the voltage at RSTZ has to cross V
TRMS
after t
DEB
is expired.
*
V
CC
or the applicable pullup voltage for the RSTZ pin.
V
TRMS
t
RST
t
DEB
RSTZ held low
b
manual switch
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

DS28DG02E-3C+

Mfr. #:
Buy DS28DG02E-3C+
Manufacturer:
Maxim Integrated
Description:
EEPROM 2Kb SPI EEPROM w/PIO RTC/Rst/Bat Mtr/Wtdg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet