DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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SPI INTERFACE
The DS28DG02 is a slave device that communicates with its master, a microcontroller, through the serial SPI
interface. This interface uses the signals CSZ (chip select), SCK (bit transfer clock), SI (serial input), and SO (serial
output). Common to SPI devices is a WPZ input (write protect), which can protect the nonvolatile bits in the SPI
Status register from inadvertent changes.
Pin Description
Chip Select (CSZ)
A low level on the CSZ pin selects the device; a high level deselects the device. A low-to-high transition on CSZ
after a valid EEPROM write sequence initiates an internal programming cycle. A programming cycle already
initiated or in progress will be completed, regardless of the CSZ input signal. When the device is deselected, SO
goes to the high-impedance state, allowing multiple parts to share the same SPI bus. After powerup, a low level on
CSZ is required prior to any sequence being initiated. The CSZ pin must remain low while the DS28DG02 is
receiving or transmitting data.
Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the DS28DG02. Instructions,
addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin
is updated after the falling edge of the clock input.
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on
the rising edge of the serial clock.
Serial Output (SO)
The SO pin is used to transfer data out of the DS28DG02. During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
Write Protect (WPZ)
The WPZ pin, if enabled, prevents writes to the nonvolatile bits in the SPI Status register. As factory default, the
WPZ pin function is disabled. This allows the user to install the DS28DG02 in a system with WPZ pin grounded and
still being able to write to the Status register. For more details see Principles of Operation.
SPI Modes and Bit Timing
The SPI protocol defines communication in full bytes with the MS bit being transmitted first. Every SPI
communication sequence begins with at least one byte written to the slave device. The first byte that the slave
receives from the master is understood as an instruction. Depending on the instruction the slave may need more
bytes, e.g., address and data; for a read function, after having received the instruction and address, the slave starts
sending data to the master.
The SPI protocol knows four communication modes, which differ in the polarity and phase of the SCK signal. The
DS28DG02 supports modes (0,0) and mode (1,1). These modes have in common that data is clocked into the
slave on the rising edge and clocked out to the master on the falling edge of SCK. The master then clocks in the
data on the rising edge of SCK. The DS28DG02 detects the mode from the logic state of SCK when CSZ gets
active (high to low transition). Therefore, SCK must be stable for the duration of a setup and hold time around the
falling edge of CSZ. Figures 9 and 10 show the timing details.
The read timing of these graphics begins with the first bit that the DS28DG02 transmits to the master and ends
when the master ends the communication by deactivating CSZ (low to high transition). The dotted line indicates the
transition between read and write, with the last bit of the command or address being clocked in on the rising edge
and the first bit of read data appearing at SO after the falling edge of SCK.
