DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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Command-Specific Communication—Color Codes
Master-to-Slave Slave-to-Master Programming
Communication Examples
Set the WEN Bit in the SPI Status Register (Write Enable)
SEL WREN DSEL
Clear the WEN Bit in the SPI Status Register (Write Disable)
SEL WRDI DSEL
Write to the SPI Status Register Sequence
SEL WREN DSEL SEL WRSR <byte> DSEL Programming
Note: It is advisable to execute a WRDI command right after the WRSR sequence is completed to ensure read
access to the user memory.
Read Status Register (e.g., to Detect the End of a Write Cycle)
SEL RDSR <byte> <byte> <byte> DSEL
Refresh PIOs with Power-On Defaults
SEL RFSH DSEL
Write 3 Bytes to User Memory Sequence, Starting Address = 067h
SEL WREN DSEL SEL WRITEL <67h> <byte> <byte> <byte> DSEL Programming
See Read Status register example to test for the end of the write cycle.
Set RTC and Calendar, Starting Address = 129h
SEL WREN DSEL SEL WRITEH <29h> <7 bytes RTC data> DSEL
SRAM, no programming time.
Read User Memory Block 1, Starting Address = 040h, 64 Bytes
SEL READL <40h> <64 bytes memory data> DSEL
Read all PIOs 3 Times, Starting Address = 126, 6 Bytes
SEL READH <26h> <6 bytes PIO data> DSEL
Continue reading until RDYZ bit is is 0
