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DS28DG02E-3C+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
7 of 34
Figure 2. Memory Map
ADDRESS TYPE ACCESS DESCRIPTION
000h to 03Fh EEPROM R/W User memory block 0.
040h to 07Fh EEPROM R/W User memory block 1.
080h to 0BFh EEPROM R/W User memory block 2.
0C0h to 0FFh EEPROM R/W User memory block 3.
100h to 109h — — Reserved, contents undefined.
10Ah EEPROM R/W Power-on default for PIO output state (PIO0 to PIO7).
10Bh EEPROM R/W Power-on default for PIO output state (PIO8 to PIO11).
10Ch EEPROM R/W Power-on default for PIO direction (PIO0 to PIO7).
10Dh EEPROM R/W Power-on default for PIO direction (PIO8 to PIO11).
10Eh EEPROM R/W Power-on default for PIO read-inversion (PIO0 to PIO7).
10Fh EEPROM R/W
Power-on default for PIO read-inversion (PIO8 to PIO11),
PIO output type (PIO0 to PIO11 in groups of 4 PIOs), PIO
output mode (same mode for all PIOs).
110h to 117h — — Reserved, contents is undefined.
118h to 11Fh ROM R 64-bit unique registration number.
120h SRAM R/W PIO output state (PIO0 to PIO7).
121h SRAM R/W PIO output state (PIO8 to PIO11).
122h SRAM R/W PIO direction (PIO0 to PIO7).
123h SRAM R/W PIO direction (PIO8 to PIO11).
124h SRAM R/W PIO read-inversion (PIO0 to PIO7).
125h SRAM R/W
PIO read-inversion (PIO8 to PIO11), PIO output type (PIO0
to PIO11 in groups of 4 PIOs), PIO output mode (same
mode for all PIOs).
126h — R PIO read access (PIO0 to PIO7).
127h — R PIO read access (PIO8 to PIO11).
128h — — Reserved, contents undefined.
129h to 12Fh NV SRAM R/W RTC and calendar.
130h to 133h NV SRAM R/W RTC alarm.
134h NV SRAM R/W Multifunction control/setup register.
135h NV SRAM R/Clear Alarm and status register.
136h and above — — Reserved, contents undefined.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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DETAILED REGISTER DESCRIPTIONS
Power-On Default for PIO Output State
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Ah
POV7 POV6 POV5 POV4 POV3 POV2 POV1 POV0
10Bh
X X X X POV11 POV10 POV9 POV8
There is general read and write access to these addresses. Factory default: 10Ah: FFh; 10Bh: 0Fh. The contents of
this register are automatically transferred to address 120h/121h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
POVn: PIO Power-On
Default State
—
Power-on default output state of PIO0 to PIO11. POV0 applies to PIO0,
etc.
X: (Not Assigned) — Reserved for future use.
Power-On Default for PIO Direction
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Ch
POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0
10Dh
X X X X POD11 POD10 POD9 POD8
There is general read and write access to these addresses. Factory default: 10Ch: FFh; 10Dh: 0Fh. The contents
of this register are automatically transferred to address 122h/123h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PODn: PIO Power-On
Default Direction
—
Power-on default direction of PIO0 to PIO11. POD0 applies to PIO0, etc.
Legend: 0 output; 1 input
X: (Not Assigned) — Reserved for future use.
Power-On Default for PIO Read Inversion (PIO0 to PIO7)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Eh
PIM7 PIM6 PIM5 PIM4 PIM3 PIM2 PIM1 PIM0
There is general read and write access to this address. Factory default: 00h. The contents of this register are
automatically transferred to address 124h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PIMn: PIO Power-On
Default Read-Inversion
—
Power-on default state of the read-inversion bit of PIO0 to PIO7. PIM0
applies to PIO0, etc.
Legend: 0 no inversion; 1 inversion
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
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Power-On Default for PIO Read Inversion (PIO8 to PIO11), PIO Output Type and Output Mode
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Fh
POTM POT3 POT2 POT1 PIM11 PIM10 PIM9 PIM8
There is general read and write access to this address. Factory default: 80h. The contents of this register are
automatically transferred to address 125h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PIMn: PIO Power-On
Default Read-Inversion
b0 to b3
Power-on default state of the read-inversion bit of PIO8 to PIO11. PIM8
applies to PIO8, etc.
Legend: 0 no inversion; 1 inversion
POT1: Power-On
Default Output Type
b4
Power-on default output type of PIO0 to PIO3;
Legend: 0 push-pull; 1 open drain
POT2: Power-On
Default Output Type
b5
Power-on default output type of PIO4 to PIO7;
Legend: 0 push-pull; 1 open drain
POT3: Power-On
Default Output Type
b6
Power-on default output type of PIO8 to PIO11;
Legend: 0 push-pull; 1 open drain
POTM: Power-On
Default Output Mode
b7
Power-on default output mode of PIO0 to PIO11;
Legend: 0 low-current, simultaneous switching; 1 high-current,
sequential switching
Unique Registration Number (118h to 11Fh)
Each DS28DG02 has a unique registration number that is 64 bits long, as shown in Figure 3. The registration
number begins with the Cyclic Redundancy Check (CRC) of the subsequent 56 bits at address 118h followed by
the 48-bit serial number (MS-byte at the lower address) and ends at address 11Fh with the family code. This CRC
is generated using the a polynomial X
8
+ X
5
+ X
4
+ 1. Additional information about CRCs is available in Application
Note 27.
Figure 3. 64-Bit Registration Number
Address 118h Addresses 119h (MSB) to 11Eh (LSB) Address 11Fh
8-Bit CRC Code 48-Bit Serial Number
8-Bit Family Code (70h)
MSB LSB MSB LSB MSB LSB
PIO Output State
ADDR b7 b6 b5 b4 b3 b2 b1 b0
120h
OV7 OV6 OV5 OV4 OV3 OV2 OV1 OV0
121h
X X X X OV11 OV10 OV9 OV8
There is general read and write access to these addresses. These registers are automatically loaded with data
from address 10Ah/10Bh when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
OVn: PIO Output State —
Output state of PIO0 to PIO11. OV0 applies to PIO0, etc.
Legend: 0 LOW; 1 HIGH if PIO direction is output
X: (Not Assigned) — Reserved for future use.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

DS28DG02E-3C+

Mfr. #:
Buy DS28DG02E-3C+
Manufacturer:
Maxim Integrated
Description:
EEPROM 2Kb SPI EEPROM w/PIO RTC/Rst/Bat Mtr/Wtdg
Lifecycle:
New from this manufacturer.
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