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SAF3560HV/V1101,51

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 13 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
[1] Table 16 defines the pin type.
[1] Table 16 defines the pin type.
Table 11. Pin description (serial NOR-Flash interface)
Symbol Pin Type
[1]
Description
HLQFP144 LFBGA170
SPI2 interface
SPI2_MI 16 F3 IZU master input of second SPI interface
SPI2_MO 17 F2 OZD master output of second SPI interface
SPI2_SCLK 18 F1 OZU serial clock output of second SPI interface
SPI2_SS1_N 19 G4 OZU slave select 1 output of second SPI interface (active LOW)
SPI2_SS2_N 20 G3 OZU slave select 2 output of second SPI interface (active LOW)
SPI2_SS3_N 22 G2 OZU slave select 3 output of second SPI interface (active LOW)
SPI2_SS4_N 23 G1 OZU slave select 4 output of second SPI interface (active LOW)
Table 12. Pin description (external host microcontroller interface)
Symbol Pin Type
[1]
Description
HLQFP144 LFBGA170
CLKOUT 1 B2 OL clock output; clock source and clock frequency are
programmable through software
RESET_N 2 B1 IZU-H master reset input from host microcontroller (active LOW)
I
2
C-bus interface (master and slave)
I2C2_DA 9 D1 IOZD-H data acknowledge input and output of the I
2
C-bus interface 2
I2C2_SCL 7 D3 IOZU serial clock input and output of the I
2
C-bus interface 2
I2C2_SDA 8 D2 IOZU serial data input and output of the I
2
C-bus interface 2
I2C1_DA 5 C1 IOZD-H data acknowledge input and output of the I
2
C-bus interface 1
I2C1_SCL 3 C3 IOZU serial clock input and output of the I
2
C-bus interface 1
I2C1_SDA 4 C2 IOZU-H serial data input and output of the I
2
C-bus interface 1
SPI1 interface
SPI1_SCLK 12 E2 IZU-H serial clock input of first SPI interface
SPI1_SI 11 E3 IZU-H slave input of first SPI interface
SPI1_SO 10 E4 OL slave output of first SPI interface
SPI1_SS_N 13 E1 IZU-H slave select input of first SPI interface (active LOW)
UART interface
UART_CTS 29 H1 IZU UART clear-to-send signal input
UART_RD 25 H3 IZU UART receive data input
UART_RTS 26 H2 OH UART ready-to-send signal output
UART_TD 24 H4 OH UART transmit data output
SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 14 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
[1] Table 16 defines the pin type.
[1] Table 16 defines the pin type.
[1] Applications, which do not need all pins from SAF3560, can treat unused pins as indicated without damage
or malfunction of the device.
Table 13. Pin description (JTAG interface)
Symbol Pin Type
[1]
Description
HLQFP144 LFBGA170
TCK 132 D6 IZU test clock input
TDI 135 A6 IZU test serial data input
TDO 136 D5 OL test serial data output
TMS 133 C6 IZU test mode select input
TRST_N 131 B7 IZU test reset input; drive LOW for normal operating
Table 14. Pin description (crystal oscillator)
Symbol Pin Type
[1]
Description
HLQFP144 LFBGA170
XTALI 141 A3 AI crystal oscillator analog input
XTALO 142 A4 AO crystal oscillator analog output
Table 15. Pin description (internally connected pins)
Symbol Pin Type Description
HLQFP144 LFBGA170
i.c. 41,
43 to 54
L5, L6, M5, M6, N1 to N6,
P3 to P5
- internally connected; leave open
Table 16. Pin type description
Type Description Unused pins
[1]
Generic pin types
AI analog input pin always connect to quartz crystal
AO analog output pin always connect to quartz crystal
G ground pin use all ground pins
IOL digital input and output; drives LOW after reset can be left open
IOZD digital input and output pin with weak pull-down can be left open
IOZU digital input and output pin with weak pull-up can be left open
IZU digital input pin with weak pull-up can be left open
OH digital output; drives HIGH after reset can be left open
OL digital output; drives LOW after reset can be left open
OZD digital output pin with weak pull-down can be left open
OZU digital output pin with weak pull-up can be left open
P power supply pin use all power supply pins
Specific pin types
-H pins with hysteresis see generic types
SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 15 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
7. Limiting values
[1] Class 2 according to JEDEC JESD22-A114.
[2] According to AEC-Q100-G.
8. Thermal characteristics
The SAF3560 has no special thermal requirements. The backside contact of the
HLQFP144 package is needed for electrical reasons. For soldering considerations, see
Section 10
.
[1] The overall R
th(j-a)
is based on JEDEC conditions and can vary depending on the board layout. To minimize the effective R
th(j-a)
, all
power and ground pins must be connected to the power and ground layers directly. An ample amount of copper area directly under the
SAF3560 with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the
effective R
th(j-a)
. In addition, the use of soldering glue with a high thermal conductance after curing is recommended.
[2] Do not use any solder-stop varnish under the chip.
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DDA(OSC)(1V2)
oscillator analog supply voltage (1.2 V) 0.5 +1.7 V
V
DDA(PLL)(1V2)
PLL analog supply voltage (1.2 V) 0.5 +1.7 V
V
DDD(C)(1V2)
core digital supply voltage (1.2 V) 0.5 +1.7 V
V
DDD(GP)(3V3)
general purpose digital supply voltage (3.3 V) 0.5 +3.9 V
V
DDD(DSP)(3V3)
DSP digital supply voltage (3.3 V) 0.5 +3.9 V
V
DDD(JTAG)(3V3)
JTAG digital supply voltage (3.3 V) 0.5 +3.9 V
V
DDD(MC)(3V3)
microcontroller digital supply voltage (3.3 V) 0.5 +3.9 V
V
DDD(SDRAM)(3V3)
SDRAM digital supply voltage (3.3 V) 0.5 +3.9 V
V
DDD(MEM)(1V2)
memory digital supply voltage (1.2 V) 0.5 +1.7 V
T
amb
ambient temperature 40 +85 C
T
stg
storage temperature 65 +150 C
V
ESD
electrostatic discharge voltage human body model
[1]
- 2000 V
charged device model
[2]
corner pins - 750 V
other pins - 500 V
I
lu
latch-up current all supply voltages
below the maximum
values listed in this
table
[2]
100 +100 mA
Table 18. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient in free air
HLQFP144
[1][2]
26.3 K/W
LBGA170 four-layer board
[1]
30 K/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

SAF3560HV/V1101,51

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Buy SAF3560HV/V1101,51
Manufacturer:
NXP Semiconductors
Description:
DIGITAL RADIO PROCESSOR 144HLQFP
Lifecycle:
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