SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 6 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration (HLQFP144)
Table 4. Pin allocation table (HLQFP144)
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 CLKOUT 2 RESET_N 3 I2C1_SCL 4 I2C1_SDA
5 I2C1_DA 6 V
DDD(MC)(3V3)
7 I2C2_SCL 8 I2C2_SDA
9 I2C2_DA 10 SPI1_SO 11 SPI1_SI 12 SPI1_SCLK
13 SPI1_SS_N 14 V
DDD(C)(1V2)
15 V
DDD(MC)(3V3)
16 SPI2_MI
17 SPI2_MO 18 SPI2_SCLK 19 SPI2_SS1_N 20 SPI2_SS2_N
21 V
DDD(MC)(3V3)
22 SPI2_SS3_N 23 SPI2_SS4_N 24 UART_TD
25 UART_RD 26 UART_RTS 27 V
DDD(C)(1V2)
28 V
DDD(MC)(3V3)
29 UART_CTS 30 SPI3_MISO 31 SPI3_MOSI 32 SPI3_SCLK
33 SPI3_SS1_N 34 V
DDD(GP)(3V3)
35 SPI3_SS2_N 36 GPIO0
37 GPIO1 38 GPIO2 39 GPIO3 40 GPIO4
41 -
[1]
42 V
DDD(GP)(3V3)
43 - 44 -
45 - 46 - 47 - 48 -
49 - 50 - 51 - 52 -
53 - 54 - 55 BB1_I2S_BCK 56 BB1_I2S_WS
57 BB1_I2S_I 58 BB1_I2S_Q 59 BB2_I2S_BCK 60 BB2_I2S_WS
61 BB2_I2S_I 62 BB2_I2S_Q 63 V
DDD(C)(1V2)
64 V
DDD(DSP)(3V3)
65 HBCKOUT 66 I2S1_O_BCK 67 I2S1_O_WS 68 I2S1_O_SD
69 BLEND 70 V
DDD(MEM)(1V2)
71 V
DDD(DSP)(3V3)
72 I2S2_O_SD
73 I2S3_O_SD/
SPDIF_O
74 I2S_I_WS 75 I2S_I_BCK 76 I2S_I_SD
77 SDRAM_DIO0 78 SDRAM_DIO1 79 SDRAM_DIO2 80 V
DDD(SDRAM)(3V3)
81 SDRAM_DIO3 82 SDRAM_DIO4 83 SDRAM_DIO5 84 SDRAM_DIO6
85 V
DDD(SDRAM)(3V3)
86 SDRAM_DIO7 87 SDRAM_DIO8 88 SDRAM_DIO9
89 SDRAM_DIO10 90 V
DDD(SDRAM)(3V3)
91 V
DDD(C)(1V2)
92 SDRAM_DIO11
SAF3560
001aah072
108
37
72
144
109
73
1
36