SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 4 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
4. Ordering information
[1] Contact NXP Sales regarding supported radio/audio DSPs: Section 14 “Contact information.
Table 2. Ordering information
Type number Package
Name Description Version
SAF3560HV/V110x HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 20 1.4 mm; exposed die pad
SOT612-4
SAF3560EL/V110x LFBGA170 plastic low profile fine pitch ball grid array package; 170 balls SOT1315-1
Table 3. Subtypes and main applications
Type number Main application Option HLQFP144 LFBGA170
SAF3560xx/V1100 HD Radio 1.0, supporting external clock from NXP
radio/audio DSPs
[1]
single tuner yes yes
SAF3560xx/V1101 HD Radio 1.0 + Conditional Access (CA) single tuner yes no
SAF3560xx/V1102 HD Radio 1.5, supporting external clock from NXP
radio/audio DSPs
[1]
dual tuner yes yes
SAF3560xx/V1103 HD Radio 1.5 + Conditional Access (CA) dual tuner yes no
SAF3560xx/V1104 HD Radio 1.0 + Conditional Access (CA), supporting
external clock from NXP radio/audio DSPs
[1]
single tuner yes yes
SAF3560xx/V1105 HD Radio 1.5 + Conditional Access (CA), supporting
external clock from NXP radio/audio DSPs
[1]
dual tuner yes yes
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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
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SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 5 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
5. Block diagram
Fig 2. Block diagram of SAF3560
001aal422
RESET_N XTAL JTAG
SDRAM
internal bus
BLEND
audio I
2
S input
3 × audio
I
2
S output
(optional S/PDIF)
SPI1 (host)
SPI2 (FLASH)
SPI3 (tuner)
2 × I
2
C-bus
GPIO
UART
baseband interface 1
(HD Radio)
baseband interface 2
(HD Radio)
SAF3560
JTAG
CONTROLLER
MEMORY
CONTROLLER
I/O
CONTROLLER
RADIO
SUB SYSTEM
DUAL
CHANNEL
RADIO
(1 × audio and
data
1 × data only)
FILTER
AND
SRC
AUDIO
SUB SYSTEM
SINGLE
CHANNEL
AUDIO
CLOCK
AUDIO
SRC
SDRAM
FLASH
CGU
I/O
MUX
RESET
SAF3560_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet Rev. 5 — 8 February 2013 6 of 24
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration (HLQFP144)
Table 4. Pin allocation table (HLQFP144)
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 CLKOUT 2 RESET_N 3 I2C1_SCL 4 I2C1_SDA
5 I2C1_DA 6 V
DDD(MC)(3V3)
7 I2C2_SCL 8 I2C2_SDA
9 I2C2_DA 10 SPI1_SO 11 SPI1_SI 12 SPI1_SCLK
13 SPI1_SS_N 14 V
DDD(C)(1V2)
15 V
DDD(MC)(3V3)
16 SPI2_MI
17 SPI2_MO 18 SPI2_SCLK 19 SPI2_SS1_N 20 SPI2_SS2_N
21 V
DDD(MC)(3V3)
22 SPI2_SS3_N 23 SPI2_SS4_N 24 UART_TD
25 UART_RD 26 UART_RTS 27 V
DDD(C)(1V2)
28 V
DDD(MC)(3V3)
29 UART_CTS 30 SPI3_MISO 31 SPI3_MOSI 32 SPI3_SCLK
33 SPI3_SS1_N 34 V
DDD(GP)(3V3)
35 SPI3_SS2_N 36 GPIO0
37 GPIO1 38 GPIO2 39 GPIO3 40 GPIO4
41 -
[1]
42 V
DDD(GP)(3V3)
43 - 44 -
45 - 46 - 47 - 48 -
49 - 50 - 51 - 52 -
53 - 54 - 55 BB1_I2S_BCK 56 BB1_I2S_WS
57 BB1_I2S_I 58 BB1_I2S_Q 59 BB2_I2S_BCK 60 BB2_I2S_WS
61 BB2_I2S_I 62 BB2_I2S_Q 63 V
DDD(C)(1V2)
64 V
DDD(DSP)(3V3)
65 HBCKOUT 66 I2S1_O_BCK 67 I2S1_O_WS 68 I2S1_O_SD
69 BLEND 70 V
DDD(MEM)(1V2)
71 V
DDD(DSP)(3V3)
72 I2S2_O_SD
73 I2S3_O_SD/
SPDIF_O
74 I2S_I_WS 75 I2S_I_BCK 76 I2S_I_SD
77 SDRAM_DIO0 78 SDRAM_DIO1 79 SDRAM_DIO2 80 V
DDD(SDRAM)(3V3)
81 SDRAM_DIO3 82 SDRAM_DIO4 83 SDRAM_DIO5 84 SDRAM_DIO6
85 V
DDD(SDRAM)(3V3)
86 SDRAM_DIO7 87 SDRAM_DIO8 88 SDRAM_DIO9
89 SDRAM_DIO10 90 V
DDD(SDRAM)(3V3)
91 V
DDD(C)(1V2)
92 SDRAM_DIO11
SAF3560
001aah072
108
37
72
144
109
73
1
36

SAF3560HV/V1101,51

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
DIGITAL RADIO PROCESSOR 144HLQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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